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The requirement of ultralow power and energy efficient systems is becoming more and more important with the increase in the use of miniaturized portable devices and unsupervised remote sensor systems. 3-D integration is an emerging technology that helps in reducing footprint as well as power. In this paper, we study in detail the combined benefits of 3-D ICs and low-voltage supply designs to obtain...
In this work we consider the suitability of Phyiscaly Unclonable Functions (PUFs) for high-security applications. For PUFs to be considered secure in such scenarios they must be resilient to both semi-invasive and fully-invasive attacks. We introduce a new failure analysis technique for semi-invasive, single-trace, backside readout of logic states. We apply this technique to characterize the unique...
Recent advances in GaN power switching devices are reviewed. A new normal-off GaN transistor called Gate Injection Transistor (GIT) increases drain current by conductivity modulation. The GIT is fabricated on cost-effective Si substrates by novel MOCVD technology enabling crack-free and smooth surfaces over 6-inch wafer. These technologies with thermally stable device isolation by Fe ion implantation...
Multiple-valued logic circuits represent nowadays a new technology challenge to realize integrated circuits using less silicon area and having low power and high frequencies characteristics. Above this technology, quaternary logic is increasingly attractive for Field Programmable Gate array devices, where the costs of area, power and interconnections delay play a key role in the overall circuit costs...
State-of-the-art device technologies of GaN power switching transistors are reviewed. The presented technologies solve the technical issues on GaN transistors for practical use replacing currently used Si-based power devices. Thick epitaxial growth over 6-inch Si substrates enables low cost fabrication of GaN devices with high breakdown voltages. A new operating principle for the normally-off GaN...
Polymer electronics, or Polytronics, as the short name, is a promising technology for low-cost and large-area electronic systems, based on novel organic materials with conducting and semiconducting properties, not addressable by conventional silicon technology. The new properties of this plastic materials are a combination of the electronic and optical properties of metals and semiconductors and the...
We present a GaN monolithic inverter IC on Si substrate and successful motor-drive by it for the first time. Taking advantages of the bi-directional operation free from the forward voltage off-set, the inverter can be operated just by the integrated six GaN-based normally-off gate injection transistors (GITs) without any external fast recovery diodes (FRDs) to flow the fly-wheel current. The IC enables...
We present a practical, systematical method for the evaluation of the soft error rate (SER) of microelectronic devices. Existing methodologies, practices and tools are integrated in a common approach while highlighting the need for specific data or tools. The showcased method is particularly adapted for evaluating the SER of very complex microelectronic devices by engineers confronted to increasingly...
The soft-error vulnerability of flip-flops has become an important factor in IC reliability in sub-100-nm CMOS technologies. In the present work the soft-error rate (SER) of a 65-nm flip-flop has been investigated with the use of alpha-accelerated testing. Simulations have been applied to study the flip-flop SER sensitivity in detail. Furthermore, an easy-to-use approach is presented to make an accurate...
With technology scaling, vulnerability to soft errors in random logic is increasing. There is a need for on-line error detection and protection for logic gates even at sea level. The error checker is the key element for an on-line detection mechanism. We compare three different checkers for error detection from the point of view of area, power and false error detection rates. We find that the double...
In this paper, we present a new technique to improve the reliability of H-tree SRAM memories. This technique deals with the SRAM power-bus monitoring by using built-in current sensor (BICS) circuits that detect abnormal current dissipation in the memory power-bus. This abnormal current is the result of a single-event upset (SEU) in the memory and it is generated during the inversion of the state of...
With the event of nanoscale technologies, new physical phenomena and technological limitations are increasing the process variability and its impact on circuit yield and performances. Like combinatory cells, the sequential cells also suffer of variations, impacting their timing characteristics. Regarding the timing behaviors, setup and hold time violation probabilities are increasing. This article...
The power consumption and the matching will be the principal issues at the 32 nm node and below. In this context, Ultra-Thin Body devices are extensively studied for the end-of-roadmap CMOS. In this paper we present the SON technology, leading to the simple fabrication of sustained mono-Si nano-membranes over an empty tunnel, and discuss on the application of this process to build-up electronic devices...
This paper introduces a novel current sense amplifier (CSA) in sub-32nm fully depleted (FD) double-gate (DG) silicon-on-insulator (SOI) technology with planar independent self-aligned gates. A new architecture is proposed which takes advantage of the back gate in order to improve circuit properties. Compared to the reference circuit, the new architecture proves to be faster (21% sensing delay decrease),...
3D contactless technology based on capacitive coupling represents a promising solution for high-speed and low power signaling in vertically integrated chips. AC coupled interconnects do not suffer from mechanical stress, and the parasitic load is much reduced when compared to standard DC solutions, such as wire bonding and micro bumps. Communication system based on wireless interconnection scheme...
In deep submicron era, to prevent larger amount of SRAM from more frequently encountered overheating problems and react accordingly for each possible hotspots, multiple ideal run-time temperature sensors must be closely located and response rapidly to secure system reliability while maintaining core frequency. This paper presented a method to extract run-time temperature information from multiple...
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