The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
Methods, algorithms and structures of neural networks were analyzed. Basic components of neural networks were defined and the principles of their development were chosen. It was shown that use of vertical-parallel method for implementation of work algorithms of neural networks basic components provides increased performance, reduce hardware costs and efficient VLSI implementation. Parallel-consequent...
We present ongoing work on a platform for mobile health and implantable telemetry devices with powerful point-of-contact processing capabilities based on our VivoSoC multi-sensor medical instrumentation SoC, a custom power management IC, and only a few additional components - allowing the realisation of sub-ccm devices. We detail the powerful yet efficient acquisition and parallel processing capabilities...
Transactional Memory (TM) promises both to provide a scalable mechanism for synchronization in concurrent programs, and to offer ease-of-use benefits to programmers. The most straightforward use of TM in real-world programs is in the form of Transactional Lock Elision (TLE). In TLE, critical sections are attempted as transactions, with a fall-back to a lock if conflicts manifest. Thus TLE expects...
Big data is a transformational force for businesses and organizations of every stripe. The ability to rapidly and accurately derive insights from massive amounts of data is becoming a critical competitive differentiator so it is driving continuous innovation among business analysts, data scientists, and computer engineers. Two of the most important success factors for analytic techniques are the ability...
Packet processing speeds in software today can hardly support the speed available on network interfaces. Consequently, many solutions that try to accelerate the processing by using programmable hardware have appeared recently. TRILL protocol is implemented by devices called RBridges which introduce Layer 3 routing features into link layer and serve for communication within a data center. However connection...
The growing complexity of digital signal processing applications make a compelling case the use of high-level design and synthesis methodologies for the implementation on reconfigurable and embedded devices. Past research has shown that raising the level of abstraction of design stages does not necessarily gives penalties in terms of performance or resources. Dataflow programs provide behavioral descriptions...
A wide variety of heterogeneous compute resources, ranging from multicore CPUs to GPUs and coprocessors, are available to modern computers, making it challenging to design unified numerical libraries that efficiently and productively use all these varied resources. For example, in order to efficiently use Intel's Knights Landing (KNL) processor, the next-generation of Xeon Phi architectures, one must...
It is beneficial to use digital circuits for data processing. Mobile devices can reduce their power consumption. This paper presents a new approach to use software descriptions to build a macroscopic circuit structure. As an example for digital signal processing the mpeg2 decoder reference implementation was transformed.
Field Programmable Gate Arrays (FPGAs) have been extensively used in accelerating applications in many digital domains, examples include image and signal processing. These applications have been abundantly tested in high level languages like C, C++ and Matlab programming. Many standard libraries exist for image processing applications like OpenCV for end to end solutions. Applications centered around...
We present a software configurable and parallelized coprocessor architecture for Linear Quadratic Regulator (LQR) control that can control physical processes representable by a linear state-space model. Our proposed architecture has distinct advantages over purely software or purely hardware approaches. It differs from other hardware controllers in that it is not hardwired to control one or a small...
Many surveys done on software developments for quaternion computation identifies floating point matrix multiplier as the most time consuming process. The floating point matrix multiplier is a highly procedure oriented process and involves computation of many partial products and storing them for final result computation. For above reason we propose a parallel matrix multiplier design which accelerates...
With the prevalence of System-on-Chips there is a growing need for automation and acceleration of the design process. A classical approach is to take a C/C++ specification of the application, convert it to a SystemC (or equivalent) description of hardware implementing this application, and perform successive refinement of the description to improve various design metrics. In this work, we present...
Data processing and combinatorial search are widely used techniques in the scope of information and communication. Examples of practical applications are sorting, frequent items encountering, matrix/set covering, graph/map coloring, data mining, priority management, and many others. Often information/data processing that involves the listed above tasks has to be done in embedded systems where high...
This paper presents an approach for exploiting multicore hardware architectures on coding level for the IEC 61131-3. An interface between the IEC 61131-3 code and software of a different programming language outsources the actual parallel workload. For validation purpose, an embedded multicore hardware is used as a controlling device, which executes software for the use case of model based condition...
We present a co-design approach to establish redundancy schemes such as Dual Modular Redundancy (DMR) and Triple Modular Redundancy (TMR) to a whole region of a processor array for a class of Coarse-Grained Reconfigurable Arrays (CGRAs). The approach is applied to applications with mixed-criticality properties and experiencing varying Soft Error Rates (SERs) due to environmental reasons, e. g., changing...
Fully Homomorphic Encryption is currently a sound theoretical approach for cloud security, it is currently not practically used due to the tremendous computation requirements of multiplying very large, million-bit, operands. In this paper, we explore the design space of software/hardware (SW/HW) co-designed accelerator relying on integrating fast software multiplication algorithms with a configurable...
Many algorithms in informatics require a set of objects with similar properties to be grouped (clustered) on the basis of some predefined criteria. The proposed technique involves hierarchical merging in which software, responsible for solving the entire problem, is enhanced with highly parallel networks in hardware accelerators. Additional improvements are achieved with the aid of support methods...
Virtualization has become one of the most helpful techniques, and today it is prevalent in several computing environments including desktops, data-centers, and enterprises. However, an I/O scalability issue in virtualized environments still needs to be addressed because I/O layers are implemented to be oblivious to the I/O behaviors on virtual machines (VM). In particular, when a multi-queue solid...
In recent years, as the development of SNS, data is produced more and more quickly. "Store-and-process", the old style of data processing is not suitable now. Obviously, stream processing systems are more capable of such tasks. But currently, these systems only run on the fixed resource, they cannot take advantage of the "pay as you go" feature which is provided by the cloud. Besides,...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.