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In this paper, we present a software approach for localization of faulty components in a 2D-mesh Network-on-Chip, targeting fault tolerance in a shared memory MP2SoC architecture. We use a pre-existing and distributed hardware infrastructure supporting self-test and de-activation of the faulty components (routers and communication channels), that are transformed into “black hole”. We detail the software...
Multi-core system is becoming the next generation embedded design platform. Heterogeneous and homogeneous processor cores integrated in Multiple Instruction Multiple Data (MIMD) System-on-a-Chip (SoC) to provide complex services, e.g. smart phones, is coming up in the horizon. However, distributed programming is a difficult problem in such systems. Today, only in very few MIMD SoC designs we can find...
This paper presents an on-line distributed induction motor monitoring system based-on the ARM (Advanced RISC Machines), which is integrated with the embedded and CAN (Controller Area Network) bus technologies. The hardware structure of the system with the ARM microprocessor S3C2410X and CAN bus controller MCP2510 is introduced, the accomplishment of software of motor on-line monitoring system is also...
As communication networks move towards 40/100G transmission capacities, wire-speed packet processing is becoming much critical to implement. Most commercial solutions for the high-speed telecom market are based on either ASIC designs and/or network processors (NPs), while enterprise solutions can eventually make use of general purpose processors (GPPs) to deal with much slower processing requirements...
This paper describes a self-configurable middleware and a node execution platform to support autonomous sensor networks. We achieve self-configuration by scheduling and strategies similar to load balancing (mapping) that is integrated in our proposed middleware. On the node execution platform we decide on the fly between microprocessor and FPGA realization of hybrid tasks. We propose a combination...
The increasing device count and design complexity are posing significant challenges to post-silicon validation. Bug diagnosis is the most difficult step during post-silicon validation. Limited reproducibility and low testing speeds are common limitations in current testing techniques. Moreover, low observability defies full-speed testing approaches. Modern solutions like on-chip trace buffers alleviate...
Evolutionary algorithms are another option for combinational synthesis because they allow for the generation of hardware structures that cannot be obtained with other techniques. This paper shows a parallel genetic programming (PGP) boolean synthesis implementation based on a low cost cluster of an embedded platform called SIE, based on a 32-bit processor and a Spartan-3 FPGA. Some tasks of the PGP...
In current Chip-multiprocessors (CMPs), a significant portion of the die is consumed by the last-level cache. Until recently, the balance of cache and core space has been primarily guided by the needs of single applications. However, as multiple applications or virtual machines (VMs) are consolidated on such a platform, researchers have observed that not all VMs or applications require significant...
Virtual platform simulation is an essential technique for early-stage system-level design space exploration and embedded software development. In order to explore the hardware behavior and verify the embedded software, simulation speed and accuracy are the two most critical factors. However, given the increasing complexity of the Multi-Processor System-on-Chip (MPSoC) designs, even the state-of-the-art...
The SHA-3 competition organized by NIST has triggered significant efforts in performance evaluation of cryptographic hardware and software. These benchmarks are used to compare the implementation efficiency of competing hash candidates. However, such benchmarks test the algorithm in an ideal setting, and they ignore the effects of system integration. In this contribution, we analyze the performance...
The Wireless Sensor Node serves as one of the crucial components needed for various wireless applications and services in the modern environment. As Wireless Sensor Networks (WSN) becomes more popular due to benefits they bring such as in smart home systems, transportation, military and etc, security issues emerge because this platform generally exposed to too many potential threats such as physical...
The research presented in this paper details a number of further novel developments to a methodology known as “Pair and Swap”. Pair and Swap is a processor-level fault tolerance technique that enables graceful degradation in multi-core chips. The new developments are based around the introduction of a, hardware-based, decision unit into the system. The decision unit is a dependable solution to the...
This paper designs a LED display system controlled by AT89C52 MCU (Microcomputer Controller Unit). The AT89C52 controls the external circuit formed by 74HC154 and 74HC595 in order to display characters, Chinese characters and figures. DS1302 is used to control the real time display. Language C is applied to compile program in Keil uVision3 programming environment. The display system is simulated through...
This paper proposes Flex Core, a hybrid processor architecture where an on-chip reconfigurable fabric (FPGA) is tightly coupled with the main processing core. Flex Core provides an efficient platform that can support a broad range of run-time monitoring and bookkeeping techniques. Unlike using custom hardware, which is more efficient but often extremely difficult and expensive to incorporate into...
The increasing failure rates observed in very deep sub micron silicon technologies pose a major problem to the design of future high-density SoCs. Emerging new architecture based on Multiprocessor SoC (MPSoC) gives the opportunity to exploit the natural redundancy with replicated spare processor in order to maintain the system performance in presence of failures. Based on the assumption that a transient...
We propose a minimalistic processor architecture tailoring Wave Field Synthesis (WFS)-based audio applications to configurable hardware. Eleven high-level instructions provide the required flexibility for embedded WFS customization. We describe the implementation of the proposed instructions and apply them to a multi-core reconfigurable WFS architecture. Our approach combines software programming...
X86 emulation on heterogeneous processor platform suffers from low performance and other problems, to solve these problems, a kind of high performance IO architecture was presented. This paper describes the design and implementations in details. At last, SPEC2000 benchmark test result showed that this IO architecture's performance is higher than the software simulation technology.
The Instruction Set Architecure (ISA) of micro-processors is usually word oriented, so it is not optimized to perform bit level operations. A functional unit oriented to the bit manipulation could accelerate the computation increasing the microprocessor performance in terms of execution time. This work presents the experimental results of the integration between the Bit Manipulation Unit (BMU) described...
As an important implementation of Cryptographic algorithm, processor should be thought about the ability of resistant power attack. In this paper we show a processor architecture, which automatically detects the execution of the encryption algorithms, and interleaves the execution of cryptographic algorithm code with that of dummy instructions to reduce the correlations between the leakage and the...
This paper proposes a security paradigm named self-existent mechanism of access control. The most distinct character is that it runs absolutely independent from program executing environment, even without cooperation of OS. That is to say, it has a unique structure to assure that computing is controlled under a secure mechanism that cannot be penetrated by software like virus, Trojan and other malicious...
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