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In this study, the effects of different influence factors on electroplating-based via-filling process were studied in a systematic manner. A through-silicon-via (TSV) chip was firstly designed, the chip size was 16 times 10 mm2 with the TSV interconnects. The via was in diameter of 50 mum and depth of 75 mum. The deep reactive ion etching (DRIE) technique was employed to fabricate the vias onto the...
One of the key technologies for developing 3-D Packaging with vertical interconnection is the interlayer metallization using formation and filling of through silicon vias. We deal with filling of via holes with diameters of 5.4-7.5 mum and depths of 47-60 mum using Cu electroplating. Prior to electroplating, the interior regions of the via holes are needed to be coated with Cu layer as a seed layer...
In this study, we fabricated in-plane thermoelectric micro-generators (4 mm times 4 mm) based on bismuth telluride thin films by using flash evaporation method. The thermoelectric properties of as-grown thin films are lower than those of bulk materials. Therefore the as-grown thin films were annealed in hydrogen at atmospheric pressure for 1 hour in a temperature range of 200 degC. to 400degC. By...
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