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In this paper, we propose a new strategy for online placement algorithm on 2D partially reconfigurable devices, termed the quad-corner (QC). The main differences between our algorithm and related art are quad-corner spreading capability and dynamical searching sequences. Moreover, existing algorithms do not evaluate their algorithms with real hardware tasks; we do experimentations with real hardware...
Dynamic partial reconfigurable FPGAs offer new design space with a variety of benefits: reduce the configuration time and save memory as the partial reconfiguration files (bitstreams) are smaller than full ones. This paper introduces a simple reconfigurable system and focuses on the advantages of the newest dynamic partial reconfiguration design flow.
In the numeric communication, much devoted efforts are dedicated to improve security and safety of numeric transactions. Hardware implementation of cryptography algorithm, as the AES, is a good solution to preserve confidentiality and accessibility to the information. In this context, this paper proposes an optimal hardware implementation of AES algorithm. Taking advantages of dynamic partially reconfigurable...
Usage of multiple supply voltages has raised new design challenges in IC design. We focus on the problem of power aware placement when dual supply voltages provide two high performance and low power working modes on each FPGA tile. To meet timing constrains, all logic elements within a tile need to work in the high performance mode when at least one element within that tile has tight timing requirements...
Based on the study of IEEE-1355 communication bus protocol in rugged environment, this paper puts forward a scheme of wormhole routing in network layer. Also a prototype of this wormhole router based on FPGA in rugged environment is designed and implemented. Experiment result shows that this solution can meet the demand of IEEE-1355 communication bus.
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