The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
As device dimensions and supply voltage are shrinking, the design of high-speed and high-resolution analog-to-digital converters (ADCs) is getting more and more challenging. Since the shrinking device sizes enable high-speed and low-power digital circuits, there has been a trend to use digital circuits to estimate and correct for the analog circuit nonidealities (i.e. calibrate) to realize high-performance...
A simple digital background-calibration technique is proposed for a pipelined analog-to-digital converter (ADC). Both gain error and DAC error are measured and calibrated by injecting two uncorrelated pseudo-random sequences into the MDAC. With this method, not only small capacitors might be used, leading to small chip size, but also the traditional current starving high gain op-amps of pipelined...
A digital foreground self-calibration method, bases on the existing off-line calibration algorithm is presented. This work extends it to correct nonlinear effects of the op amps. It eliminates both linear and nonlinear errors, such as capacitors mismatch, comparator offset, finite op amp gain error, and op amp nonlinearity. The simulation shows that this work gives great improvements of 38.25dB and...
This paper describes a mixed mode background calibration technique for pipeline analog-to-digital converter (ADC). The proposed calibration scheme uses an insignificant, low-speed, low-power, high-resolution sigma-delta ADC to determine error in digital domain. The calibration technique calibrates capacitor mismatch as well as finite opamp dc gain, while the digital redundancy compensates for comparator...
The pipelined architecture is one of the most popular analog-to-digital converter (ADC) architectures. Various circuit nonidealities such as finite opamp gain and mismatch in capacitors limit the pipelined ADCpsilas performance. In this paper, a new technique for the calibration of interstage gain errors in pipelined ADCpsilas are described. The proposed calibration scheme uses a slow but accurate...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.