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In this paper we discuss about 3 general issues on mesh topology in “networks on chip” (NOC): Utilizing multi-level mesh for delay reduction, using route by considering the mesh topology concept, and finally an optimal model of mesh topology named “multi-level mesh topology” which is defined based on 5-layer network model is suggested. In multi-level mesh topology we can see that this architecture...
Topology has significant effects on the most important parameters of a network such as latency and power consumption. The sphere based topology is a new structure for Network-on-Chips that forms in sphere shape. We have used a Zone-Order label based algorithm for the routing that is a general algorithm for routing requirements, and it is based on spanning tree. We have compared sphere based topology...
Network on chip (NoC) is an effective solution to complex on-chip communication problem. The mesh topology is one of the most popular NoC. It has completely regular topology which can be implemented easily, but the communication delay between remote nodes is large. In this paper, we propose an improved topology called Tmesh, which is based on the standard mesh network by inserting four long links...
Networks-on-Chip (NoC) have emerged as a replacement for traditional shared-bus designs for on-chip communications. As with all current VLSI design, however, reducing power consumption in NoCs is a critical challenge. One approach to reduce power is to dynamically scale the voltage and frequency of each network node or groups of nodes (DVFS). Another approach to reduce power consumption is to replace...
Three-dimensional (3D) silicon integration technologies have provided new opportunities for Network-on-Chip (NoC) architecture design in Systems-on-Chip (SoCs). In this paper, we consider the application-specific NoC architecture design problem in a 3D environment. We present an efficient floorplan-aware 3D NoC synthesis algorithm, based on simulated allocation, a stochastic method for traffic flow...
Network delay is a major design parameter for Networks-on-Chip (NoC)-based applications. Improving NoC delay could be achieved at different design phases. At the system level, we study in this paper the impact of the network topology on NoC system delay using graph-theoretic concepts. A topology-based model is developed to calculate the average NoC delay, which is caused by links and routers. The...
Fault tolerant routing algorithms, are a key concern in on-chip communication. This paper examines fault tolerant communication algorithms for use in network-on-chip (NoC). We propose an improved wormhole-switched routing algorithm in 2-dimensional mesh based on f-cube3 algorithm to decrease message latency. The existing key concept is using numbers of virtual channels (VC) via a physical link. This...
The design of scalable and reliable interconnection networks for multicore chips (NoCs) introduces new design constraints like power consumption, area, and ultra low latencies. Although 2D meshes are usually proposed for NoCs, heterogeneous cores, manufacturing defects, hard failures, and chip virtualization may lead to irregular topologies. In this context, efficient routing becomes a challenge....
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