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The paper presents an efficient parallel timing synchronization algorithm structure, which is suitable for high speed communications demodulation system and easy to implement on FPGA platform. First, a new parallel timing synchronization structure is displayed. Wherein the proposed parallel structure make up of a feedback loop based on the farrow interpolation filter, Gardner algorithm and the numerically...
In this paper, image processing algorithms designed in Zynq SoC using the Vivado HLS tool are presented and compared with hand-coded designs. In Vivado HLS, the designer has the opportunity to employ libraries similar to OpenCV, a library that is well-known and wide used by software designers. The algorithms are compared in terms of area resources in two conditions: using the libraries and not using...
The EEG pre-processing steps involve removing noise and artifacts from EEG. The noise from the main source like electro-oculogram, electrocardiogram, electromyogram and other sources should be eliminated to increase accuracy in classification. As these artifacts may be misinterpreted as originating from the brain, there is a need to minimize or remove them from recorded EEG signals. The artifacts...
In order to reduce the noise content of the fiber optic gyro (FOG) output signal, and to improve the zero drift index of the FOG, the paper uses the programmable logic device FPGA. The LMS algorithm is analyzed and studied, and it is realized by Verilog language programming. The thought of the paper is based on classical finite state machine. Compared with previous programming algorithms, it has a...
This paper presents a FPGA (Field Programmable Gate Array)-based remotely sensed imagery denoising method, named FPGA-based median filtering. The proposed method is capable of processing large volume data since it takes full advantages of FPGA hardware and abundant logic units. This paper first overviews the traditional median filtering algorithm, and then highlights the FPGA-based filtering, including...
Impulse noise is introduced into images in the process of image acquisition and transmission. High density impulse noise suppression using median type filters result worst where as these execute better to suppress the low density impulse noise from corrupted images. Some state of art methods are able to remove high density impulse noise from corrupted images but sometimes the detail of images are...
Median filtering is a well-known method used in a wide range of application, especially for the removal of salt and pepper noise. It can reduce noise effectively while keeping the edges. Currently, existing algorithms give good results, but theirs efficiency need to be improved in some real-time applications. In this paper, we propose a neighborhood processor implementation of fixed size kernel median...
Nuclear spectrum is the important information in domain of nuclear physics research. Radiation detection and applications of nuclear technology, nuclear spectrum measurement technique have been a hot issue. And one of the key technologies of digital nuclear spectrum measurement technology is how to achieve digital filter-shaping algorithm on the digital processing device. Base on Sallen-Key filter...
In PCM/FM remote sensing receiving system, when the bit rate is above 1Mbps, the signal suffers frequency select fading, which causes the serious inter-symbol interference (ISI); power allowance can no longer guarantee the system quota. Besides signal reflection such as buildings, ground, mountains and atmospheric refraction eventually become the multipath interference signals. Thus an adaptive filter...
This paper presents post-processing algorithms which work on a commercial FPGA for high quality stereo vision results. Specially, in this paper we focus the description of algorithms and their performance evaluation results instead of explaining hardware architecture. The proposed algorithms consists of five sub-blocks in cascade manner, which are consistency check, hole filling, variance check, weighted...
In order to implement real-time image preprocessing and fast phase calculating problem, this paper presents a hardware circuit structure by making use of FPGA (Field Programmable Gate Array). This hardware circuit structure can solve the real-time fast problem of image preprocessing and phase calculating. By using look ahead multiplier, median filter, IP Core, etc. we build a hardware circuit algorithm...
To improve the speed of the image processing chip, to quick share the market and to reduce costs, this paper designs a chip with Harvard Architecture and FPGA. The chip is also used with a new hardware algorithm. Using the chip, the processing time is 13.2% less than the time of the chip with Von Neumann Architecture. The used units of filter are 13% of the whole FPGA gates, less than the claim part...
Information-theoretic cost functions such as minimization of the error entropy (MEE) can extract more structure from the error signal, yielding better results in many realistic problems. However, adaptive filters (AFs) using MEE methods are more computationally intensive when compared to conventional, mean-squared error (MSE) methods employed in the well-known, least mean squares (LMS) algorithm....
With the improvement of the performance of ADC, it is available to sample and process real signal in intermediate frequency in radio communication system design. The large source usage and long latency of image-reject filter and decimation in IF DDC are the difficult problems in design. But In many occasions the signal can be processed as narrow band signal. In this paper, we designed an M-points...
Median filter has good capabilities for reducing a variety kind of random noise, and causes less ambiguity than linear smoothing filters under same processing size. In order to suppress the impulse noise of digital video signal and meet the system's needs of real-time, it is of great significance to do fast filtering of image based on hardware. By analyzing the common 3×3 filtering window's mathematical...
For blocking pornographic, illegal websites by Intenet host domain, now the majority of solutions are based on the identification and blocking by software. Basing on the analysis of Bloom Filter algorithm and combining with the feature of FPGA chip, this paper proposes an efficient, high-speed hardware-based Implementation of the host domain blocking.
We present a new approach to designing multi-mode FIR filters in FPGAs based on partitioning a design into shared, mode-independent blocks and reconfigurable, mode-specific regions. We also provide a theoretical formulation for finding an optimal sequence of modes that minimizes a joint cost function related to area and reconfiguration overhead. Our results show that for a group of template matching...
This paper discusses the FPGA implementation of modified Goertzel Algorithm for the application of DTMF signal detection, which is as effective as that of normal Goertzel Algorithm yet is more resources saved than that of normal Goertzel Algorithm. Detail algorithm simulation and algorithm FPGA implementation are given in the paper.
Principle of image edge detection system and advantages of FPGA technique in processing speed and exploitation period are discussed briefly and feasibility based on Sobel operator to implement image edge detection is analyzed. Coprocessor module of image edge detection with EDA+FPGA technique is presented to meet the real-time request of image edge detection. Synthesis and waveform simulation prove...
This paper presents a design flow for the generation of optimized FIR filters. It includes a graphical interface to integrate the complete synthesis flow, from the filter specification to a synthesizable VHDL. This allows the user to quickly develop high performance filters that meet the design constraints. The designed software supports coefficient and data bit-width configuration at design time...
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