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Simultaneous switching noise (SSN, also called delta-I noise) has become a tremendous challenge to the reliable operation of high speed electronic circuits. Etching narrow slots on the power or ground plane is one of the efficient techniques to isolate the SSN. A new method for modeling SSN of power-ground planes with narrow slot is proposed in this paper. Firstly, the gapped power-ground planes characteristic...
This paper reports a new recursive algorithm for efficient estimation of the noise content in time-domain noise analysis of non-linear dynamic integrated circuits with arbitrary excitations. Statistical simulation of specific circuit fabricated in 65 nm CMOS process shows that the proposed algorithm offers accurate and efficient solution.
A time-domain methodology for noise analysis of non-linear dynamic integrated circuits with arbitrary excitations is presented. A non-stationary stochastic noise process is described as an Ito system of stochastic differential equations and a numerical solution for such a set of equations is found. Statistical simulation of specific circuits fabricated in 65 nm CMOS process shows that the proposed...
This paper proposes a Volterra-enhanced model to evaluate the impact of substrate noise on CMOS regenerative comparators and on flash A/D converters. The presented approach initially extends the linear model of the non-uniform sampling (NUS) distortion of the comparator due to substrate noise, to include 2nd and 3rd order non-linearities. The effectiveness of the enhanced model is then evaluated by...
Requirement of image recovery in IC detection is rising. IC noise image recovery technology based on three-dimensional energy optimization modeling and surface fairing is investigated. By spatial vector's deduction of image's noise point, modeling and fairing of IC image noise's surface from three-dimensional information is achieved. Through surface extraction and fairing that smooth image plane can...
Noise performance of the switched source follower (SSF) track and hold (T/H) circuit is analyzed. Approximate expressions for the output noise of the track mode and hold mode of the T/H circuit are derived respectively. Simulations based on a commercial available 65 nm process technology are implemented with the SpectreRF circuit simulator. It is shown that the noise contribution from the parasitic...
With the continuous increase of chip complexity and blocks density, the conventional substrate noise optimization tools which are based on some substrate noise models will consume a period of unbearable time. Further more, all the tools only aim at decreasing the total noise but ignore the specific constraints of analog parts such as symmetry constraint. In this paper, we first prove the effectiveness...
We consider a current source driver macromodel approach for the fast solution of a combined on-chip driver-interconnect model problem. In this approach, we divide the problem into two separate parts which are solved independently so that the nonlinear solution is only required for a small portion of the overall problem.
This paper proposes a new approach to analyze crosstalk of coupled interconnects in the presence of process variations. The suggested method translates correlated process variations into orthogonal random variables by principle component analysis (PCA). combined with polynomial chaos expression (PCE), the technique utilizes Stochastic Collocation Method (SCM) to analyze the system response of coupled...
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