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Replacement of an electric vehicle conventional Si-IGBT traction inverter with a SiC-MOSFET inverter can achieve reductions in urban driving cycle average loss by a factor of four, reduction in peak loss by a factor of three, and reduction in semiconductor die area by a factor of two. An 80 kW EV powertrain based on the Nissan LEAF is modeled in MATLAB/Simulink, and EPA standard driving cycles such...
Power vs efficiency analysis of High-Frequency Wireless Power Transfer Systems (WPTSs) is discussed in this paper. The adopted model includes the effects of modulation of the duty-cycle and phase-shift of the secondary side controlled rectifier, as well as parameters mismatches of resonant elements, which influence the power losses of both rectifier and inverter semiconductor devices. The global influence...
This paper introduces the failure operation principle of the capacitive floating level shifter, as well as its simplified circuit model. Based on the model, the mathematical equations for analyzing the level shifter's characteristics and its respective performances are also derived. Design criteria for the capacitive floating level shifter are proposed derived from the model and corresponding MATLAB...
This paper proposes a power train structure including a CSI with an integrated buck-converter to feed an IPMSM for automotive application. An optimized operation strategy to 1) extend the base speed range and 2) maximize the system efficiency is introduced. Simulated system performance and efficiency are presented and compared to the conventional VSI-based power train.
Due to the very large difference between electrical and thermal time constants, stimulation for resonantly operated DC-DC converters using physical or ideal switching model is very time-consuming or impossible with limited computational resources. In order to overcome this problem a novel thermal-electrical averaging model of resonantly operated DC-DC converters is proposed in this contribution. The...
The paper presents a detailed study on the idle leakage reduction techniques on partially depleted silicon-on-insulator (PD-SOI) CMOS SRAM. The most promising leakage reduction techniques that have been proposed are introduced, analyzed and compared into 65 nm low-power PD-SOI technology, taking into account all the SOI specific effect. Especially, it is shown that the leakage reduction techniques...
While the CMOS analog circuits can be designed with the minimum-gate-length of the fabrication process in the alpha-power law MOSFET model, the length of a MOSFET gate has been chosen to be a larger scale than the minimum-gate-length in the conventional Shockleypsilas square model. In this paper, we describe a 6-b 100 MSPS CMOS current steering digital-to-analog converter (DAC) with the alpha-power...
Current mode (CM) scheme provides suitable alternative for the high speed on-chip interconnect signaling. This paper presents a energy-delay optimization methodology for the current-mode (CM) signaling scheme. Optimization for the CM circuits for on-chip interconnects requires a joint optimization of driver and receiver device sizes, as their parameters which affect the energy-delay performance depend...
A novel methodology for accurate and efficient static timing analysis is presented in this paper. The methodology is based on finding a frequency domain model for the gates which allows uniform treatment of the gates and interconnects. It is shown that despite the highly nonlinear overall gate model, a frequency domain model of the gate with the model parameters, gate moments, as functions of the...
This paper presents an analytical modeling of ballistic and quasi-ballistic transport, implemented in Verilog-A environment and used for circuit simulation. Our model is based on the Lundstrompsilas approach and uses an expression of the backscattering coefficient given by the flux method. The model takes also into account short channel effects and tales into account the effects of different scattering...
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