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In this paper, we investigate the design of binary tree multipliers based on multi-input counters using hybrid MOS and single-electron transistors (SETs). Our focus is on the design of phase-modulated counters which can be implemented with only a few MOSFETs and multi-gate SETs. In order to address some practical issues associated with SET/MOS hybrid circuits, we present an enhanced version of the...
Negative Bias Temperature Instability (NBTI) of pMOSFETs is nowadays the most prominent device degradation mechanism reported in the literature and a limiting factor for CMOS technology scaling. In contrast, for Positive Bias Temperature Instability (PBTI) of pMOSFET only very few publications can be found [1–4]. Most of the PBTI work is done for nMOSFETs from process nodes employing high-K dielectrics...
NBTI (Negative Bias Temperature Instability), which can degrade the switching speed of PMOS transistors, has become a major reliability challenge. Meanwhile, reducing leakage consumption has become major design goals. In this paper, we propose a novel transmission gate-based (TG) technique to minimize NBTI-induced degradation and leakage. This technique provides higher flexibility compared to the...
NBTI degradation mechanism is studied for 0.18µm pMOSFETs. Degradation on saturation and linear mode of operations are investigated respectively. To address the controlled delay in between stress cycles which account for the recovery effect, an optimized ID-VG sweep is devised in this work. The optimized ID-VG sweep is found to be able to reduce the recovery effect and it is easily to be implemented...
The minimum operating voltage (Vmin) of nano-scale LSIs is investigated, focusing on logic gates, SRAM cells, and DRAM sense amplifiers in LSIs. The Vmin that is governed by SRAM cells rapidly increases as devices are miniaturized due to the ever-larger variation of the threshold voltage (VT) of MOSFETs. The Vmin, however, is reduced to the sub-one-volt region by using repair techniques and new MOSFETs...
The dramatic increase in leakage current, coupled with the swell in process variability in nano-scaled CMOS technologies, has become a major issue for future IC design. Moreover, due to the spread of leakage power values, leakage variability cannot be neglected anymore. In this work an accurate analytic estimation and modeling methodology has been developed for logic gates leakage under statistical...
Continuous scaling, necessary for enhanced performance and cost reduction, has pushed existing CMOS materials much closer to their intrinsic reliability limits, forcing reliability engineers to get a better understanding of circuit failure. This requires that designers will have to be very careful with phenomena such as high current densities or voltage overshoots. In addition to the reliability issues,...
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