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This paper proposes to provide testability for the breaking point produced by the Through-Silicon-Vias (TSVs) of 3D-Stacked ICs (3D-SICs) during pre-bond testing with low Design-for-Testability (DfT) cost. Different from prior solutions which utilize two additional wrapper cells for the breaking point at each TSV, this paper proposes to provide the testability of two ends of the TSVs respectively...
With continued scaling, reliability is emerging as a critical challenge for the designers of digital circuits. The challenge stems in part from the lack of computationally efficient techniques for analyzing and optimizing circuits for reliability. To address this problem, we propose an exact analysis method based on circuit transformations. Also, we propose a hybrid method that combines exact analysis...
We present a practical, systematical method for the evaluation of the soft error rate (SER) of microelectronic devices. Existing methodologies, practices and tools are integrated in a common approach while highlighting the need for specific data or tools. The showcased method is particularly adapted for evaluating the SER of very complex microelectronic devices by engineers confronted to increasingly...
For several decades, the output from semiconductor manufacturers has been high volume products with process optimisation being continued throughout the lifetime of the product to ensure a satisfactory yield. However, product lifetimes are continually shrinking to keep pace with market demands. Furthermore there is an increase in dasiafoundrypsila business where product volumes are low; consequently...
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