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We present a novel computing model that allows to conveniently construct multi-core systems with different computer architectures, ranging from homogeneous many-core architectures to networks of heterogeneous general purpose processor cores or signal processing engines. A hardware library implemented on Field Programmable Gate Arrays (FPGAs) and a compiler provide a platform for prototyping and constructing...
The eikonal partial differential equation is solved using a modified level set algorithm which is then transformed into a proposed field programmable gate array implementation. The numerical method for isotropic material eikonal hardware engines is extended to angle dependent anisotropic media in two dimensions. This new method transforms the eigenvalue iteration into a process which executes in constant...
This paper presents several challenges and solutions in designing an efficient Message Passing Interface (MPI) implementation for embedded FPGA applications. Popular MPI implementations are designed for general-purpose computers which have significantly different properties and trade-offs than embedded platforms. Our work focuses on two types of interactions that are not present in typical MPI implementations...
High-performance reconfigurable computers (HPRC) provide a mix of standard processors and FPGAs to collectively accelerate applications. This introduces new design challenges, such as the need for portable programming models across HPRCs, and system-level verification tools. In this paper, we extend previous work on TMD-MPI to include an MPI-based approach to exchange data between X86 processors and...
With the recent emergence of multicore architectures, the age of multicore computing might have already dawned upon us. This shift might have triggered the evolution of von Neumann architecture towards a parallel processing paradigm. Cellular Automata- inherently decentralized spatially extended systems consisting of large numbers of simple and identical components with local connectivity, also proposed...
We describe the implementation of a hardware-accelerated particle graphics engine on a reconfigurable computer. The engine incorporates a configurable flow model that enables the simulation of complex spatially-dependent particle graphics effects. The FPGA particle engine was designed using the Mitrion-C high-level language, and did not require detailed hardware design. The engine was implemented...
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