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In this paper, we propose an adaptive truncate k-bit re-configurable approximation (aTra) method which can achieve similar video coding efficiency as the original transform but substitute all low efficient multiplication by conformed shifting and addition operations, lifting the utilization of the hardware implementation and making simple hardware implementation and high efficiency pipeline design...
This work proposes a cascaded and pipelined (CAP) reconfigurable architecture to achieve high throughput in executing numerical reduction operations commonly found in many scientific computations by (1) cascading multiple deeply-pipelined floating-point arithmetic cores to match the inherent computing structure underlying target operations, (2) interleaving multiple computing threads to eliminate...
Due to the continuously decreasing cost of FPGAs, they have become a valid implementation platform for SOCs. Typically, a soft core processor implementation is used to execute the software parts of the SOC. As each system is individually designed for a particular application, the idea is natural to support compute intensive parts of the code through customized hardware acceleration. Two different...
Static and dynamic variations, which have negative impact on the reliability of microelectronic systems, increase with smaller CMOS technology. Thus, further downscaling is only profitable if the costs in terms of area, energy and delay for reliability keep within limits. Therefore, the traditional worst case design methodology will become infeasible. Future architectures have to be error resilient,...
The increase in the complexity of a wide-issue processor with its pipeline width is one of the primary concerns of processor designers. In the conventional design, the hardware in the processor core is laid out to handle multiple instructions with two source operands in each pipeline stage. However, an analysis of SPEC2000 programs reveals that an integer program on the average constitutes 25.2 percent...
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