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In this paper, we present a new technique for highly efficient terrain rendering using continuous view-dependent Level-of-Detail based on hardware tessellation unit found in modern GPUs. Our technique is based on parallel local processing, in the sense that the results at each terrain patch do not depend on results already obtained at other patches. This patch-by-patch processing uses no hierarchical...
Many important software applications are dominated by non-trivial serial components: Amdahl's Law places a hard upper bound on possible speedup that can be achieved for these applications. In this paper, we propose an integrated software/hardware approach for accelerating hard serial bottlenecks in data structure heavy algorithms. The key idea is to overlap the processing of the main algorithmic functions...
Instruction set accelerator architectures have emerged recently as light-weight hardware coprocessors, so as to transparently improve applications performance. This paper investigates the effectiveness of adding hardware accelerators as refers to scaling, based on applications that show data level parallelism such as image edge detection and fractal applications. The implementation results using reconfigurable...
There is building interest in using FPGAs as accelerators for high-performance computing, but existing systems for programming them are so far inadequate. In this paper we propose a soft processor programming model and architecture inspired by graphics processing units (GPUs) that are well-matched to the strengths of FPGAs, namely highly-parallel and pipelinable computation. In particular, our soft...
By a rapid development of graphics processing unit (GPU), the programmability and highly parallel processing feature of GPU create a chance to allow the general purpose computation to be conducted on GPU, conventionally called GPGPU (general purpose computation on GPU). A brief survey, in particular on the rationale of how the GPU architecture leads to GPGPU, is introduced in this paper, and various...
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