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The paper deals with very accurate and effective simulation of Complementary Metal-Oxide-Semiconductor (CMOS) transistors which are used to construct basic logic gates (inverter, NAND and NOR) and their composites (XOR, AND, OR). The transistors are substituted by a resistor-capacitor (RC) circuit and the circuit is described by a system of differential algebraic equations (DAEs). These equations...
Muller C-element is one of the main parts of an asynchronous circuit. Being sequential by its nature, it is vulnerable to single event upsets (SEU). We propose three 65 nm CMOS circuit implementations of SEU tolerant C-element, whose tolerance is achieved by using of well-known DICE principle and is proved by SPICE simulations and semi-empirical estimations.
Radiation-induced Single Event Transients (SETs) have the potential to create metastability in asynchronous circuits, as they are much shorter than the typical handshake cycle and do not respect the timing closure. Micropipelines have been shown to be effective in filtering those pulses. In this paper1 we investigate the propagation of pulses of critical width through a micropipeline in SPICE simulations...
As technology is scaled down, supply voltage and gate capacitances are reduced which degrades the reliability of the circuits. For near sub-threshold region design, this causes even more serious reliability issues because the supply voltage is reduced to near the threshold voltage of the devices. Soft error is one such phenomenon which changes internal node voltage due to external noise. Hence it...
Embedded systems account for wide range of applications. However, the design of such systems is faced with a diverse spectrum of criteria. The energy consumption, performance, and demanding security concerns are some of the most significant challenges in designing of such systems. With these challenges, the design process can be managed more easily if a flexible logic circuit with the ability of satisfying...
Integrated CMOS-circuits are built up out of small stages which contain a few devices only. Particularly in integrated analog circuits the majority of these small stages have to be modified for every application regarding to their altered electrical boundary conditions. This usually ends up in a complete new revision of circuit sizing for the stages resp. the total circuit. However, this sizing process...
In this paper we investigate the effectiveness of iDDT-based testing in detecting resistive open defects for future CMOS technologies down to 22 nm taking into consideration the wide process variations associated with such technologies. The SPICE parameters that we use for such advanced models are taken from the predictive technology model (PTM) and the ranges of process variations are taken from...
A novel register, in which MTJ device is centered, is proposed in this paper. Based on the demand of MTJ's reading and writing process, some additional devices have been integrated with the MTJ device to compose the actual structure. It has been simulated using Hspice and the simulated result shows that it can be operated as a register in the circuit. Moreover, the layout of the register based on...
A piecewise linear delay model is accurate to within plusmn10% of SPICE over a wide range of the input transition time. Model accuracy has improved by taking into account the effect of the input slope and short circuit current. Comparisons with SPICE simulation has been observed in several test circuits.
Finite element device level simulations were used in conjunction with SPICE modeling to design and optimize a complementary MOS inverter circuit with an organic p-type and an inorganic n-type transistor combination. The device characteristics of the p-type and the n-type transistors were generated through 2D finite element device level simulations. The drain current (ID) vs. drain-source voltage (V...
We present a practical, systematical method for the evaluation of the soft error rate (SER) of microelectronic devices. Existing methodologies, practices and tools are integrated in a common approach while highlighting the need for specific data or tools. The showcased method is particularly adapted for evaluating the SER of very complex microelectronic devices by engineers confronted to increasingly...
The implementation of complex functionality in low-power nano-CMOS technologies leads to enhance susceptibility to parametric disturbances (environmental, and operation-dependent). The purpose of this paper is to present recent improvements on a methodology to exploit power-supply voltage and temperature variations in order to produce fault-tolerant structural solutions. First, the proposed methodology...
With technology scaling, vulnerability to soft errors in random logic is increasing. There is a need for on-line error detection and protection for logic gates even at sea level. The error checker is the key element for an on-line detection mechanism. We compare three different checkers for error detection from the point of view of area, power and false error detection rates. We find that the double...
While the CMOS analog circuits can be designed with the minimum-gate-length of the fabrication process in the alpha-power law MOSFET model, the length of a MOSFET gate has been chosen to be a larger scale than the minimum-gate-length in the conventional Shockleypsilas square model. In this paper, we describe a 6-b 100 MSPS CMOS current steering digital-to-analog converter (DAC) with the alpha-power...
Current mode (CM) scheme provides suitable alternative for the high speed on-chip interconnect signaling. This paper presents a energy-delay optimization methodology for the current-mode (CM) signaling scheme. Optimization for the CM circuits for on-chip interconnects requires a joint optimization of driver and receiver device sizes, as their parameters which affect the energy-delay performance depend...
This paper studies the impact of intra-die random variability on low-power digital circuit designs, specifically, circuit timing failures due to intra-die variability. We identify a new low-Vdd statistical failure mode that is strongly supply-voltage dependent and also introduce a simple yet novel method for quantifying the effects of process variability on digital timing - a delay overlapping stage...
This paper describes a design flow for the circuit-level optimization of a technology. The concurrent exploration of device characteristics and library design choices leads to a more application-optimal technology. We illustrate the design flow by: 1) analyzing the impact of buffer cell design, and 2) by optimizing a 130 nm technology for low operational power.
Channel carriers in MOSFETs accelerated by high drain fields can generate electron hole pairs which are detected by measuring the substrate current. In switching operation the maximum substrate current only flows during a short time. Results of static and dynamic measurements and a model for circuit simulators (e.g. SPICE) are presented.
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