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The design and implementation of a lossless compression system for hyperspectral images on a processor-plus-field-programmable gate array (FPGA)-based embedded platform. Software execution time of compression algorithm was profiled first to conclude the decision of accelerating the most time consuming interband prediction module by hardware realization. Efficient algorithm to hardware mapping led...
Packet Classification involves matching information from a packet's header to a set of rules in a database in order to determine the manner in which the packet should be processed by network processors. The PCIU algorithm is a novel classification algorithm which improves upon previously published techniques in the literature. The main features of the PCIU algorithm are the low pre-processing time...
Parameterisable configurations allow very fast run-time reconfiguration in FPGAs. The main advantage of this new concept is the automated tool flow that converts a hardware design into a more resource-efficient run-time reconfigurable design without a large design effort. In this paper, we show that the automated tool flow for run-time reconfiguration can be used to easily optimize a full hardware...
Neuromorphic engineering tries to mimic biological information processing. Address-Event-Representation (AER) is an asynchronous protocol for transferring the information of spiking neuro-inspired systems. Currently AER systems are able sense visual and auditory stimulus, to process information, to learn, to control robots, etc. In this paper we present an AER based layer able to correct in real time...
In this paper, a motion control IC for linear motor drive X-Y table using FPGA (Field programmable gate array) technology is presented. Firstly, the mathematical model of the X-Y table is defined. Secondly, an adaptive fuzzy controller (AFC) is introduced and adopted in position loop of X-Y table to improve the motion tracking performance under unmodelled uncertainty condition. Thirdly, in implementation,...
Partial reconfiguration (PR) offers the possibility to adaptively change part of the FPGA design without stopping the remaining system. In this paper, we present a comprehensive framework for adaptive computing, in which design key points of hardware processes, system interconnections, operating systems (OS), device drivers, scheduler software as well as context switching are respectively concerned...
Efficient and reliable verification system is requested for a system-on-chip (SOC) design before it is committed to production. The intention of the paper is to judge whether our hardware/software (HW/SW) co-verification system can handle SOC verification and provide the necessary performance in terms of co-verification speed and throughput. A finite impulse response (FIR) filter is utilized as a...
The advance in FPGA technology allowed embedding different types of resources on a single chip. These resources range from a simple look-up table to a complete processor. The resources available on the FPGA fabric allow building various hardware systems for different applications with several trade-offs in terms of performance and power consumption. This paper proposes six different architectures...
Use of two-dimensional memory array for lookup table (LUT) based reconfigurable computing frameworks has been proposed earlier for improvement in performance and energy-delay product (EDP). In this paper, we propose an integrated solution for achieving significantly higher EDP in these frameworks by leveraging on the read-dominant memory access pattern. First, we propose to employ an asymmetric memory...
As the use of FPGAs increases, the importance of highly optimized processors for FPGAs will increase. In this paper we present the microarchitecture of a soft microprocessor core optimized for the Virtex-4 architecture. The core can operate at 357 MHz, which is significantly faster than Xilinxpsila Microblaze architecture on the same FPGA. At this frequency it is necessary to keep the logic complexity...
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