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Hardware acceleration is a popular method to boost performance in video processing applications. This paper shows how to accelerate such applications on a general-purpose CPU by means of a coprocessor that is tightly-coupled to the instruction pipeline. A method for efficient data transfer between CPU and coprocessor is developed, and the resulting data path architecture with optimum scheduling of...
In HW/SW co-simulation based logic verification systems, the design under test (DUT) is executed on an FPGA based emulator and the behavioral testbench written in some high level language like C or HDL is run on a SW simulator or a general purpose CPU. In such systems it is essential to reduce the communication between SW and HW sides to enhance overall verification speed. Therefore it is of significant...
rSesame is a generic modeling and simulation framework which can explore and evaluate reconfigurable systems at the early design stages. The framework can be used to explore different HW/SW partitionings, task mappings and scheduling strategies at both design time and runtime. The framework strives for a high degree of flexibility, ease of use, fast performance and applicability. In this paper, we...
Reconfigurable computing systems allow executing tasks in a true multitasking manner. Such systems share the reconfigurable device and processing unit as computing resources which leads to highly dynamic allocation situations. To manage such systems at runtime, a reconfigurable operating system is needed. The main part of this operating system is resource management unit which performs HW/SW partitioning,...
The RTOS (Real-Time Operating System) is a critical component in the SOPC (System-On-Programmable-Chip), in which the hardware-software unified multi-task management and scheduling of RTOS can significantly improve the performance of SOPC. First, we build a unified scheduling policy based on hardware-software unified multi-task management model. Then, we analyze the shared resources competition problem...
Reconfigurable computers (RC) can provide significant performance improvement for domain applications. However, wide acceptance of todaypsilas RCs among domain scientist is hindered by the complexity of design tools and the required hardware design experience. Recent developments in hardware/software co-design methodologies for these systems provide the ease of use, but they are not comparable in...
Dynamic run-time scheduling of design modules in partial reconfigurable (pRTR) platforms have recently become an active area. The pRTR integration in System-on-Chips depends on the efficiency of the technique for scheduling the modules. In this paper, an event based dynamic scheduling technique for hardware emulation is proposed. In consideration of given functional modules (e.g. controller, signal...
A formal methodology for automatic hardware-software partitioning and co-scheduling between the muP and the field programmable gate array (FPGA) has not yet been established. Current work in automatic task partitioning and scheduling for the reconfigurable systems strictly addresses the FPGA hardware, and does not take advantage of the synergy between the microprocessor and the FPGA. In this research,...
A formal methodology for automatic hardware-software partitioning and co-scheduling between the muP and the FPGA has not yet been established. Current work in automatic task partitioning and scheduling for reconfigurable systems strictly addresses the FPGA hardware, and does not take advantage of the synergy between the microprocessor and the FPGA. In this work, we consider the problem of co-scheduling...
Current work on automatic task partitioning and scheduling for reconfigurable computing (RC) systems strictly addresses the FPGA hardware, and does not take advantage of the synergy between the microprocessor and the FPGA. Efforts on partitioning between muP and the FPGA are a manual and laborious effort, as a formal methodology for automatic hardware-software partitioning has not been established...
In this paper, we present a multiobjective hardware-software cosynthesis system, called SLOPES, for multirate low-power real-time distributed embedded systems consisting of dynamically reconfigurable field-programmable gate arrays (FPGAs), processors, and heterogeneous communication resources. This cosynthesis algorithm simultaneously optimizes system price and average power consumption. First, we...
This paper describes the hardware/software co-design of a multithreaded RTOS kernel on a new Xilinx Virtex II Pro FPGA. Our multithreaded RTOS kernel is an integral part of our hybrid thread programming model being developed for hybrid systems which are comprised of both software resident and hardware resident concurrently executing threads. Additionally, we provide new interrupt semantics by migrating...
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