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Throughput is a key performance metric for streaming FFT architectures. However, increasing spatial parallelism to improve throughput introduces complex routing, thus resulting in high power consumption. In this paper, we propose a high throughput energy efficient parallel FFT architecture based on Cooley-Tukey algorithm. Multiple pipeline FFT processors using time-multiplexing are utilized to perform...
We consider a new generation of COTS software routers (SRs), able to effectively exploit multi-Core/CPU HW platforms. Our main objective is to evaluate and to model the impact of power saving mechanisms, generally included in today's COTS processors, on the SR networking performance and behavior. To this purpose, we separately characterized the roles of both HW and SW layers through a large set of...
We consider a new generation of COTS software routers (SRs), able to effectively exploit multi-core/CPU HW platforms. Our main objective is to analyze, to evaluate and to model the impact of power saving mechanisms, generally included in today's COTS processors, on the SR behavior and networking performance. To this purpose, we tried to understand and to separately characterize the roles of both HW...
This paper presents SmartCell as a novel power efficient reconfigurable architecture targeted for data streaming applications. We describe the design details of the SmartCell architecture, including processing element, reconfigurable interconnection fabrics, instruction and control process and dynamic configuration scheme. The performance in terms of power efficiency and system throughput is evaluated...
For the next generation of multi-core processors, the on-chip interconnection networks must be efficient to achieve high data throughput and performance. Moreover, these interconnections must be flexible and scalable in order to provide parallel on-demand computing. For this reason, the goal of this paper is to present design decisions of a multi-cluster NoC (MCNoC) architecture in order to support...
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