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Direct Digital Frequency Synthesizer (DDFS) circuits are routinely implemented in many electronic systems. Advanced DDFS design techniques have been proposed and optimized for ASIC (Application Specific Integrated Circuits) implementations. Nowadays, FPGA devices are frequently chosen as target for digital circuits. This paper presents the FPGA implementation of state of the art DDFS architectures...
A comparison of two novel P1619 XTS-AES architectures, is presented in this paper. Two of the architectures are introduced for the first time and are aiming in either cost- or performance-efficient operation. The implementations are based on the use of a single or dual AES cores for simultaneous Tweak value calculation and block encoding/decoding operations.
A novel modular multiplier is implemented on FPGA for elliptic curve cryptography (ECC) over GF(p). First, using the embedded 18??18-bit multipliers in the FPGA device, we design a 256-bit Montgomery modular multiplier which spends 3 clock cycles to compute a modular multiplication. Second, the algorithm for Karatusba-Ofman multiplication is used to reduce the number of embedded multipliers needed...
Executing various combinations of external locating techniques provides many benefits over tracking and locating systems based on radar or GPS. These embedded radio positioning applications are built on a common set of functional capabilities. Development of a specific positioning system involves selection of a subset of these capabilities and implementation into a physical form that meets the size,...
This study was to analyze the performance of fixed-point adaptive signal enhancer (ASE) for somsatosensory evoked potential (SEP) measurement. An animal study was conducted to evaluate the usefulness of this technique in detection of spinal cord injury. The ASE technique has been reported powerful to improve signal to noise ratio of SEP. Therefore, we proposed an integrated circuit module to perform...
Embedded computing platforms have long incorporated non-traditional architectures (e.g., FPGAs, ASICs) to combat the diminishing returns of Moore's Law as applied to traditional processors. These specialized architectures can offer higher performance potential in a smaller space, higher power efficiency, and competitive costs. A price is paid, however, in development difficulty in determining functional...
It is difficult to model all effects of magnetic channel for performance simulations. Verifying in a real environment becomes especially critical when algorithms rely on special properties of the Read/Write Channel (RWC) for magnetic recording systems. A self contained flexible FPGA based prototype platform has been developed for RWC digital architecture and performance evaluation for Hard Disk Drive...
Field programmable gate arrays (FPGAs) have been available for more than 25 years. Initially they were used to simplify embedded processing circuits and then expanded into simulating application specific integrated circuit (ASIC) designs. In the past few years they have grown in density and speed to replace ASICs in some applications and to assist microprocessors as attached accelerators. This paper...
Clock performance becomes a challenge in Structure ASIC world when system performance requirement keep increasing and logic density grows rapidly. In general, clock performance is evaluated through the clock skew and the clock integrity. The difficulty in ensuring minimum clock skew while maintaining clock integrity becomes more challenging when the device size grows and clock frequency increases...
The implementation of a recently proposed IP core of an efficient motion estimation co-processor is considered. Some significant functional improvements to the base architecture are proposed, as well as the presentation of a detailed description of the interfacing between the co-processor and the main processing unit of the video encoding system. Then, a performance analysis of two distinct implementations...
In this paper, we present a novel technique for online testing of feedback bridging faults in the interconnects of the cluster based FPGA. The detection circuit will be implemented using BISTER configuration. We have configured the Block Under Test (BUT) with a pseudo-delay independent asynchronous element. Since we have exploited the concept of asynchronous element known as Muller-C element in order...
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