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FPGA is widely used in military and aerospace applications and FPGA testing is the most effective means to ensure the reliability of them. Interconnect Resources testing is one of the most important parts of FPGA testing since that most of the faults occur on Interconnect Resources. FPGA needs to be configured as specified circuits before being tested and conventional HDL-based configuration can not...
This paper addresses a synthesis process of VHDL code for FPGA design flow using Xilinx PlanAhead tool. This tool provide a low power profile, more hard IP functionality, create a global timing constraint, lower node capacitance & architectural innovations, cost of development, very high DSP performance hardware solutions and easily can be evolutionary algorithms, reconfigured to the development...
Configurable logic blocks and programmable interconnections realize configurable computing. This paper proposes a configurable CMOS H-tree logic module. The module consists of a front-end, local programmable mesh and a CMOS H-tree circuit. The small, local mesh is used for 4-variable inverted input signals. The 18-transistor (9P9N) CMOS H-tree logic module could build two-input universal functions,...
We propose and analyze an organization for a field-programmable gate array structure that operates using a balanced ternary logic system where the logic set {??1, 0} maps directly to equivalent voltage levels {??1.0V, 0.0V}. Circuits for basic components such as a ternary buffer, flip-flop and LUT are described based on the characteristics of a commercial silicon-on-sapphire process that offers multiple...
Due to their reconfigurability and their high density of resources, SRAM-based FPGAs are more and more used in embedded systems. For some applications (Pay-TV,Banking, Telecommunication ...), a high level of security is needed. FPGAs are intrinsically sensitive to ionizing effects, such as light stimulation, and attackers can try to exploit faults injected in the downloaded configuration. Previous...
Field programmable gate arrays (FPGAs) are getting more and more attractive for military and aerospace applications, among others devices. The usage of non volatile FPGAs, like Flash-based ones, reduces permanent radiation effects but transient faults are still a concern. In this paper we propose a new methodology for effectively measuring the width of radiation-induced transient faults thus allowing...
In this paper, we present a novel technique for online testing of feedback bridging faults in the interconnects of the cluster based FPGA. The detection circuit will be implemented using BISTER configuration. We have configured the Block Under Test (BUT) with a pseudo-delay independent asynchronous element. Since we have exploited the concept of asynchronous element known as Muller-C element in order...
Radiation Test Consortium (XRTC) single-event measurements for three of the latest generation of radiation-tolerant reconfigurable FPGAs from Xilinx (90 nm, copper- interconnected, thin-epitaxial CMOS) are presented. Results include proton and heavy-ion upset susceptibilities for unclocked memory elements, high-temperature latchup immunity and a low SEFI rate (e.g., ~one/device-century in geosynchronous...
In this paper we discuss optimizing the interconnect power of designs implemented in FPGA platforms. In particular, we reduce the glitch power on interconnects associated with the output of functional units in a design. The idea is to activate unused flip-flops to block the propagation of glitches, which takes advantage of the abundant flip-flops in modern FPGA structures. Since the activation of...
Field programmable dual-Vdd interconnects are effective to reduce FPGA power. Assuming uniform length interconnects, existing work has developed time slack budgeting to minimize power based on estimating the lower bound of power reduction using dual-Vdd for given time slack. In this paper, we show that such lower bound estimation cannot be extended to mixed length interconnects that are used in modern...
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