Serwis Infona wykorzystuje pliki cookies (ciasteczka). Są to wartości tekstowe, zapamiętywane przez przeglądarkę na urządzeniu użytkownika. Nasz serwis ma dostęp do tych wartości oraz wykorzystuje je do zapamiętania danych dotyczących użytkownika, takich jak np. ustawienia (typu widok ekranu, wybór języka interfejsu), zapamiętanie zalogowania. Korzystanie z serwisu Infona oznacza zgodę na zapis informacji i ich wykorzystanie dla celów korzytania z serwisu. Więcej informacji można znaleźć w Polityce prywatności oraz Regulaminie serwisu. Zamknięcie tego okienka potwierdza zapoznanie się z informacją o plikach cookies, akceptację polityki prywatności i regulaminu oraz sposobu wykorzystywania plików cookies w serwisie. Możesz zmienić ustawienia obsługi cookies w swojej przeglądarce.
In this paper, we push the limits in maximizing the throughput of side-channel-protected AES-GCM implementations on an FPGA. We present a fully unrolled and pipelined architecture that uses a Boolean masking countermeasure (specifically, threshold implementation) for first-order DPA resistance. Using a high-end Virtex-7 device, we obtain a throughput of 15.24 Gbit/s. Since masked implementations require...
The secrecy of information predominantly relies on secrecy of used cryptographic key rather than secrecy of cryptographic algorithm. Thus, a very important component of cryptographic system verification is proofing that cipher text originates from given plain text and specified cryptographic key. The implementation of such methodology is complex in bulk mode transmission systems with multi Gbit/s...
The Advanced Encryption Standard (AES) together with the Galois Counter Mode (GCM) of operation has been approved for use in several high throughput network protocols to provide authenticated encryption. However, the demand for continued increase in network bandwidth has not abated and we anticipate the need for continual performance improvement of AES-GCM in hardware. Additionally, as data interfaces...
Memory systems security has increased over the last decade due to the sensitive information which is stored in plain text. Device specific attacks, such as cold-boot and side-channel monitoring have been reported as being successfully in retrieving encryption and private keys from algorithms like AES and RSA. In this paper, we propose a new technique of securing the cache memories by scrambling the...
In this paper, we present the design of a cryptographic core compliant with the IEEE 802.15.4 standard and based on FPGA. We have addressed several security problems that remain yet problematic concerning the implementation of the 802.15.4 security suites and the access control list (ACL). The cryptographic core consists of three components: a compact AES-CCM architecture, a content-addressable memory...
This paper describes two high-performance reconfigurable hardware implementations of the Data Encryption Standard (DES) algorithm. This is achieved by combining pipelining concept with time-variable key technique. The two proposed schemes change the key with time. The first one uses a counter to change the key every clock cycle. The second changes the key using a pseudorandom number generator. Using...
The forthcoming IEEE 802.3ba Ethernet standard will provide data transmission at a bandwidth of 100 Gbit/s. Currently, the fastest cryptographic primitive approved by the U.S. National Institute for Standard and Technology, that combines data encryption and authentication, is the Galois/Counter Mode (GCM) of operation. If the feasibility to increase the speed of the GCM up to 100 Gbit/s on ASIC technologies...
In this paper, the implementation and reconfigurable feature of RSA and AES cryptographic algorithm are analyzed. On the basis of the Reconfigurable design of this two algorithms, Reconfigurable RSA and AES hardware architecture is designed to fit four different key length of 256bit, 512bit, 1024bit, 2048bit for RSA, and three different key length of 128bit, 192bit, and 256bit for AES. The reconfigurable...
In this paper, we provide a low cost AES core for ZigBee devices which accelerates the computation of AES algorithms. Also, by embedding the AES core, we present an efficient architecture of security accelerator satisfying the IEEE 802.15.4 specifications. In our experiments, we observed that the AES core and the security accelerator use fewer logic gates and consume lower power than other architectures...
Podaj zakres dat dla filtrowania wyświetlonych wyników. Możesz podać datę początkową, końcową lub obie daty. Daty możesz wpisać ręcznie lub wybrać za pomocą kalendarza.