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Authentication and encryption within an embedded system environment using cameras, sensors, thermostats, autonomous vehicles, medical implants, RFID, etc. is becoming increasing important with ubiquitious wireless connectivity. Hardware-based authentication and encryption offer several advantages in these types of resource-constrained applications, including smaller footprints and lower energy consumption...
Many applications use encryption to protect data confidentiality, which require decryption before any data processing. Integrating ASIC design of encryption engines and general-purpose processor can yield the best overall performance in program execution as it benefits from low latency hardware engine and high processor memory bandwidth. However, ASIC design is fixed once manufactured, which cannot...
This paper proposes a solution to improve the security of the partial dynamic reconfiguration of FPGA, without significantly affecting the reconfiguration performance. The existing solutions for secure partial dynamic reconfiguration on SRAM based FPGAs impact the reconfiguration process and the available resources due to their complex multi-layered partial bitstream validation process. This adversely...
Advancements in silicon, software and IP support have made Field Programmable Gate Arrays (FPGAs) a highly flexible solution for many applications. With the growing number of companies providing IP support for FPGAs, IP license violations by over-deployment of IP into more devices than originally licensed remains a major concern for IP owners. In this paper we present a solution for secure IP exchange...
High throughput AES encryption/decryption is a necessity for many of modern embedded systems. This article presents a high performance yet cost efficient AES system. Maestro can be used in a wide range of embedded applications with various requirements and limitations. Maestro is about one million times faster than the pure software implementation. The Maestro architecture is composed of two major...
This paper presents a hardware architecture for secure quadrotor communication. Both, the control data sent by the ground station and the information data sent by the quadrotor are encrypted and authenticated. The system is implemented on an FPGA and integrated on an extension board. The board is embedded into a self-constructed quadrotor based on the project Next-Generation Universal Aerial Video...
This paper discusses design and analysis of an FPGA-based system containing two isolated, Altera Nios II softcore processors that share data through two custom crypto-engines. FPGA-based Single-Chip Cryptographic (SCC) techniques were employed to ensure full red/black separation. Each crypto-engine is a hardware implementation of the Advanced Encryption Standard (AES), operating in Galois/Counter...
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