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CMOS utilizing high mobility III-V/Ge channels on Si substrates is expected to be one of key devices for high performance and low power advanced LSIs in the future. In addition, the heterogeneous integration of these materials on the Si platform can provide a variety of applications from high speed logic CMOS to versatile SoC chips, where various functional devices can be co-integrated. In this presentation,...
We have developed 90nm In0.7Ga0.3As channel HEMTs, directly measured of DC and RF characteristics, and performed microwave modeling for both 90nm Si CMOS and HEMT for benchmarking logic performance for future design layout and process improvement.
III-V/Ge CMOS on Si platform, realized by heterogeneous integration, is expected to provide a variety of applications from high speed logic CMOS to versatile SoC chips, where various functional devices can be co-integrated. Among them, we are currently pursuing high speed/low power logic CMOS using III-V/Ge channels. While many critical issues have been well recognized for them, we present possible...
With the consideration of III-V channels for future CMOS, an urgent need for standard metrics to assess the maturity of III-V MOSFETs and to investigate their suitability for future CMOS has arisen. By proposing such standard metrics (Q ≡gm/S), we find that present InGaAs n-MOSFETs are trailing Si MOSFETs by over a factor of 30. Still, experimental PHEMT data make a clear case for the utilization...
To address the integration of the high-mobility Ge/III-V MOSFET, a common gate stack (CGS) solution is proposed for the first time and demonstrated on Ge and InGaAs channels with combined hole and electron field-effect mobility values up to 400 cm2/eV-s and 1300 cm2/eV-s. Based on the duality found on the InGaAs/Ge MOS system, this approach aims to integrate the InGaAs/Ge MOSFET processes for high...
III-V compound semiconductors have received renewed attention as the channel materials for future generation CMOS technology. High performance long-channel GaAs MOSFETs and short-channel InGaAs MOSFETs are demonstrated. High current of 960 muA/mum and transconductance of 793 muS/mum have been achieved. Scaling behavior has been investigated experimentally down to 80 nm for the first time in III-V...
The surface Fermi level unpinning in InGaAs has been realized with high kappa dielectric growth using molecular beam eitaxy (MBE) and atomic layer deposition (ALD). Furthermore, world-record device performances in self-aligned inversion-channel InGaAs MOSFET and a capacitance equivalent thickness (CET) of les 1 nm in Ga2O3(Gd2O3) and ALD-HfO2 on InGaAs have been achieved.
A physics-based analytical compact model of InGaAs FETs for logic applications is developed. This model neither heavily depends on parameter extraction nor requires any time-consuming computation, enabling digital circuit design and circuit-level performance estimation for III-V FETs. The model captures SCE, trapezoidal well QW energies and capacitances including 2D potential profile information.
In this paper, high-performance inversion-type E-mode In0.53Ga0.47As and In0.65Ga0.35As MOSFETs with ALD Al2O3 as gate dielectric is demonstrated and systematically studied their subthreshold or weak inversion characteristics. Much more works are needed to make this novel device structure a competitive technology for ultimate CMOS at 22 nm node or beyond. The work is supported by National Science...
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