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In this paper, the application of an asymmetric independent-gate MOSFET (IG-MOSFET) to the bit-cell structures of the SRAM schemes that were previously proposed using the symmetric IG-MOSFET is analyzed. In addition, a novel SRAM scheme with the asymmetric IG-MOSFET is proposed to improve read stability and writeability by controlling the back gates of pass-gate and pull-up transistors. New array...
This paper presents a new SRAM memory cell in Double Gate MOS technology. It's a reconfigurable 6T-4T that takes benefit of the advantages of both 6T and 4T SRAM cells. The cell improves both read stability and write-ability, without adding any transistor or external signal, compared to conventional 6T SRAM cell. The write ability is improved by a factor of 64% and the stability in read mode by a...
The power consumption and the matching will be the principal issues at the 32 nm node and below. In this context, Ultra-Thin Body devices are extensively studied for the end-of-roadmap CMOS. In this paper we present the SON technology, leading to the simple fabrication of sustained mono-Si nano-membranes over an empty tunnel, and discuss on the application of this process to build-up electronic devices...
This paper introduces a novel current sense amplifier (CSA) in sub-32nm fully depleted (FD) double-gate (DG) silicon-on-insulator (SOI) technology with planar independent self-aligned gates. A new architecture is proposed which takes advantage of the back gate in order to improve circuit properties. Compared to the reference circuit, the new architecture proves to be faster (21% sensing delay decrease),...
Novel 3D stacked gate-all-around multichannel CMOS architectures were developed to propose low leakage solutions and new design opportunities for sub-32 nm nodes. Those architectures offer specific advantages compared to other planar or non planar CMOS devices. In particular, ultra-low IOFF (< 20 pA/mum) and high ION (> 2.2 mA/mum) were demonstrated. Moreover, those transistors do not suffer...
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