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Low-density parity-check (LDPC) codes are known for superior performance over a wide range of codes for communication and memory systems. In many practical scenarios, adaptive ECC system is preferred that can adapt to various codes with varying channel conditions since the behavior of errors changes with time and space. This paper presents two architectural designs for efficient encoding of LDPC codes...
High-performance storage class memories could benefit from a fast decoding error correcting code (ECC), able to correct a few errors in just a few nanoseconds. The class of BCH codes provides excellent candidates to play this role. The low latency requirement prevents adopting iterative or sequential processes in the encoding and decoding phases—as traditionally done for storage application based...
A 32kb memory is presented with an Ultra Low Voltage optimized 10 transistors bitcell designed to withstand an extended voltage range from 1.2V down to 0.35V, achieving 1.77pJ low energy access. A validation circuit was fabricated in 65nm CMOS and exhibits wafer level yield above 95% at 0.4V, 1MHz. Packaged parts show 0.32V minimum voltage at 490kHz and up to 17X energy gain per operation. The memory...
Non-binary low-density parity-check (NB-LDPC) codes can achieve better error-correcting performance than their binary counterparts when the code length is moderate. Check node processing is one bottleneck in NB-LDPC decoding. Various techniques have been proposed to simplify the check node processing. Particularly, the computation complexity can be reduced by employing an iterative forward-backward...
Modern high-performance processors utilize cache memory systems to tolerate the increasing latency of main memory. Along with IC technology improvement, complicated cache memory systems in processors are very vulnerable to soft errors under severe environment. To deal with multiple soft errors with little impact on hardware overhead and performance, this paper proposes a new cache memory system, in...
This paper presents a multiword based error correction code (MECC) scheme to mitigate SEUs in low-voltage SRAMs. MECC combines four 32 bit data words to form a composite 128 bit ECC word and uses optimized transmission-gate XOR logic, thus significantly reducing check-bit overhead and error correction time, respectively. Use of composite word warrants a unique write operation where MECC updates checkbits...
In this paper, we present a new technique to improve the reliability of H-tree SRAM memories. This technique deals with the SRAM power-bus monitoring by using built-in current sensor (BICS) circuits that detect abnormal current dissipation in the memory power-bus. This abnormal current is the result of a single-event upset (SEU) in the memory and it is generated during the inversion of the state of...
This paper describes a methodology for building a reliable internet core router that considers the vulnerability of its electronic components to single event upset (SEU). It begins with a set of meaningful system level metrics that can be related to product reliability requirements. A specification is then defined that can be effectively used during the system architecture, silicon and software design...
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