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Computing modular multiplication over GF(2m) is often a performance critical operation in cryptographic applications. This paper describes the architecture of a scalable and configurable Montgomery modular multiplier over binary fields. This architecture, implemented on a FPGA platform, aims to reduce the computation time thanks to the pipelining of the datapath. Scalability is achieved by allowing...
In this paper, a solution to support the run-time read back, relocation and replication of cores in embedded systems with dynamic and partial reconfiguration capabilities is presented. The proposal shows a peripheral structure that allows an easy integration and communication with the rest of the system, including an API to make the reconfiguration details to be more transparent to software applications...
In this paper, a design of a dual symbol processor for arithmetic coder architecture implemented on FPGA is proposed. Usually, the regular operation of the MQ-Coder is sequential, which can process only one symbol at a time. However, the bit-plane coding can generate more than one symbol per clock cycle. Consequently, the coding speed will be limited and bottlenecked at the interface between the output...
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