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This paper presents a novel memory cell design as a variant of Lior Atias' 13T cell (mentioned as LA13T cell in this paper) for low-voltage operation and ultra-low power space applications. Using C-element as a replacement of dual-driven inverters in the LA13T cell, our proposed radiation hardened by design memory cell (referred to as RHD13T) can effectively block the unwanted paths from Vdd to Gnd...
A low-power high-speed two-stage dynamic comparator is presented. The voltage fluctuation at the first stage of the comparator (pre-amplifier stage) is limited to Vdd/2. Therefore, the power consumption of the first stage which is the dominant part of the total power consumption is reduced. The output voltage of the first stage is kept above Vdd/2. As a result, during the comparison the second stage...
This paper devotes to a new 5-2 compressor designed according to a new architecture with a pure Glitchless output. A considerable increase in the speed of the operation is achieved by utilizing a new truth table, fast production of signals Cout1 and Cout2, optimum tuning of the width of the utilizing transistors, and eliminating the parasitic capacitances through merging the drain of transistors....
Many existing XOR-XNOR cells suffer from nonfull-swing outputs, high power consumption and low speed issues. In this paper, a new fast, full-swing and low-power XOR-XNOR cell, is presented. Simulation results in 90-nm CMOS technology show that the proposed circuit has rail to rail outputs Also, we have gained 11%–51%, 2%–19% and 18%–52% improvement in delay, power consumption and power-delay product...
This paper proposes an all-digital temperature sensor (ADTS) with a ring oscillator for achieving the following goals: 1) high accuracy; 2) high resolution; 3) low power-supply sensitivity; and 4) low cost. The sensor was developed using a 0.18-$\mu \text{m}$ standard CMOS process with a 1.8-V supply voltage. The measured results indicate that the proposed ADTS generates a Pearson correlation coefficient...
Noise is an important factor in the analog and digital circuits which determine the characteristics of the system. The work aims at developing a noise robust circuit with high frequency response and the same can be implemented in a dynamic logic system with reduced number of transistor and also the dynamic logic will have the probability of signal switching activity to be low which will subsequently...
This paper devotes to a new 7-2 compressor designed according to a new architecture with a pure Glitchless output. A considerable increase in the speed of the operation is achieved by utilizing a new truth table, fast production of signals Cout1 and Cout2, optimum tuning of the width of the utilizing transistors, and eliminating the parasitic capacitances through merging the drain of transistors....
A novel level-up shifter with dual supply voltage is proposed. The proposed design significantly reduces the short circuit current in conventional cross-coupled topology, improving the transient power consumption. Compared with the bootstrapping technique, the proposed circuit consumes significantly less area, making it more practical for ICs with a large number of supply voltages. The minimum power-delay...
Analysis of the operation of CMOS gates is a complicated procedure. These gates can be replaced by equivalent inverters and therefore the expressions for the inverters are used to determine the electrical characteristics of the gates. In this paper, the equivalent inverter approach for replacing CMOS gates is evaluated. The NAND gate is used for this evaluation. Parametric expressions are created...
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