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The embedded block coding with optimized truncation (EBCOT) is a key algorithm in JPEG 2000 image compression system. Various applications, such as medical imaging, satellite imagery, digital cinema, and others, require high speed, high performance EBCOT architecture. Though efficient EBCOT architectures have been proposed, hardware requirement of these existing architectures is very high and throughput...
In this paper, a field-programmable gate array (FPGA) based enhanced architecture of the arithmetic coder is proposed, which processes two symbols per clock cycle as compared to the conventional architecture that processes only one symbol per clock. The input to the arithmetic coder is from the bit-plane coder, which generates more than two context-decision pairs per clock cycle. But due to the slow...
Because of serial inherence of the arithmetic encoder (AE) for the embedded block coding algorithm in JPEG2000, efficient hardware implementation of AE plays a key role in overall system throughput. In this paper, four pipelined architectures which are single-symbol coding 3-stage pipeline, single-symbol coding 4-stage pipeline, two-symbol coding 3-stage pipeline and two-symbol coding 4-stage pipeline,...
Because of the feedback loops caused by iterative operations, MQ arithmetic coder usually acts as the performance bottleneck of the hardware architecture for JPEG2000 algorithm. According to the different features of the loops, this paper adopts different optimizing methods rather than general concurrent techniques to improve the hardware efficiency as well as throughput. Based on careful analysis...
A novel subblock-based scheme for bit plane encoder (BPE) of EBCOT in JPEG2000 is presented to conquer the mismatch in access pattern to code block memory. A codeblock is partitioned into 4 times 4 subblocks and encoded subblock by subblock; each subblock is encoded as the traditional scheme. The new scheme is compatible to existing accelerating technologies, such as sample-parallel, pass-parallel,...
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