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Injecting faults into designs is a way to qualify a verification environment. To improve the performance of a qualifying process, we need to remove identical faults. The problem will provide some faulty design cases; the contestants must identify all sets of identical faults. The judgment will be based on correctness, execution time and memory usage. The topic mainly belongs to gate level design.
In this paper, a method for generating test patterns for sequential circuits while designing the circuits is presented. By the aim of this approach, hardware designers can obtain test patterns for their sequential designs while designing the circuit by an HDL, without any need of software languages and reformatting the design for evaluation and application of test generation methods. PLI (Procedural...
Recently, a new test point insertion method for pseudo-random built-in self-test (BIST) was proposed in [Yang 09] which tries to use functional flip-flops to drive control test points instead of adding extra dedicated flip-flops for driving the control points. This paper investigates methods to further reduce the area overhead by replacing dedicated flip-flops which could not be replaced in [Yang...
In this paper, we propose a new search technique for ATPG, called CONCAT [1], which (a) is based on AND/OR reasoning, (b) integrates conflict driven learning, and (c) avoids over specification of test vectors. The technique works seamlessly (i) between Boolean and non-Boolean gates in industrial designs, (ii) across phases in latch-based designs, (iii) between justification and propagation tasks in...
We propose a built-in scheme for generating all patterns of a given deterministic test set T. The scheme is based on grouping the columns of T, so that in each group of columns the number ri of unique representatives (row subvectors) as well as their product R over all such groups is kept at a minimum. The representatives of each group (segment) are then generated by a small finite state machine (FSM)...
The implementation of complex functionality in low-power nano-CMOS technologies leads to enhance susceptibility to parametric disturbances (environmental, and operation-dependent). The purpose of this paper is to present recent improvements on a methodology to exploit power-supply voltage and temperature variations in order to produce fault-tolerant structural solutions. First, the proposed methodology...
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