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A fully-integrated, 3-5 GHz Impulse-Radio UWB transceiver with on-chip flash ADC is designed in 90 nm-CMOS. A new scheme for receiver phase acquisition is proposed that uses pulse injection-locking to synchronize the receive clock with the transmitted data, eliminating the need for clock/data recovery (CDR), requiring only static receiver phase alignment with the transmitted pulses at startup. Transmitter...
A transceiver for communicating over an electronic textiles medium is implemented for body area networks. A supply-rail-coupled differential signaling scheme permits time-sharing of the eTextiles medium between communication and remote powering circuits. Fabricated in 0.18 μm CMOS and operating at 0.9 V, the chip consumes 110 μW at a data rate of 10 Mb/s over a 1 m fabric link.
We report a receiver for ten-level pulse-amplitude modulated (10-PAM) encoded data signals, which was measured to receive data at 8 Gb/s at a maximum frequency (2 GHz). To increase data bit-rate and reduce BER, we designed this circuit by using a current mode amplifier, high speed comparator and a current-mode logic (CML) circuit. The 10-PAM receiver is designed in 0.18 ??m CMOS technology. The measured...
3D contactless technology based on capacitive coupling represents a promising solution for high-speed and low power signaling in vertically integrated chips. AC coupled interconnects do not suffer from mechanical stress, and the parasitic load is much reduced when compared to standard DC solutions, such as wire bonding and micro bumps. Communication system based on wireless interconnection scheme...
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