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In a scan-based test architecture, the scan power and and test data volume can be reduced by utilizing a double tree scan (DTS) architecture. This paper presents a novel hardware implementation of the DTS architecture and compares the hardware overhead with the conventional scan architecture. The implementation proposed utilizes a clock structure which greatly decreases the number of clocked flip-flops...
Recent work on random access scan (RAS) has shown its advantages in reducing test application time, test data volume and test power over those of the conventional serial scan (SS). This paper is first to examine the soft error tolerance of RAS. The RAS structure not only improves error tolerance ability during test, it also provides capability to efficiently enhance the circuits error tolerance during...
Hardware accelerators are common in embedded systems that have high performance requirements but must still operate within stringent energy constraints. To facilitate short time-to-market and reduced non-recurring engineering costs, automatic systems that can rapidly generate hardware bearing both power and performance in mind are extremely attractive. This paper proposes the BLADES (Better-than-worst-case...
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