The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
The common solution for a field programmable gate array (FPGA)-based time-to-digital converter (TDC) is constructing a tapped delay line (TDL) for time interpolation to yield a sub-clock time resolution. The granularity and uniformity of the delay elements of TDL determine the TDC time resolution. In this paper, we propose a dual-sampling TDL architecture and a bin decimation method that could make...
Delay defects can be detected using Launch-off-capture (LOC) and Launch-off-shift (LOS) based delay test techniques. In terms of delay test coverage and test set size, LOS is more effective compared to LOC. However, to exercise LOS test a high speed scan enable signal is required. The cost of implementing a high speed global scan enable signal is prohibitively high. In practice, most of the commercial...
A low-jitter and wide output frequency range ADPLL was proposed in this paper. The adopted PFD based on sense-amplifier flip-flop (SAFF) can effectively improve the jitter performance. The novel DCO with cascading structure consists of a coarse-tuning delay chain and a fine-tuning interpolator, obtaining both wide frequency tuning range and high resolution. A time-amplifier based sub-exponent TDC...
This paper introduces a design independent extension to RTL-to-GDS design-flows for seamless insertion of timing-detection flip-flops at critical paths of a digital CMOS standard-cell circuit. It is possible to detect timing-errors for general purposes at any critical path including enable-inputs of clock-gating cells with typically 15% area overhead for 20% endpoint coverage while maintaining DFT...
An approach to test application called transparent scan provides an opportunity to share tests among different logic blocks whose primary inputs and outputs are included in scan chains even if the blocks have different numbers of state variables. The conventional methodology suffers from problems such as high power consumption, less quality results both in terms of pattern count and fault coverage...
The Clock gating reduces dynamic power dissipation in synchronous circuits. The gating function is the process of filtering glitches from a block which is achieved by inserting clock gating cell. Clock gating logic uses strong and weak matching process, they are two kinds of factor form matching. The strong matching seeks for the matches which are externally present in the factored forms and the weak...
In this article partial products algorithm of serial multipliers is presented and different architectures of these kinds of multipliers such as: Successive Addition, Serial-Parallel and Serial-Serial methods are surveyed. With respect to extension capability of pipeline architecture, this circuit is implemented as 4-bit serial-serial multiplier. Some problems have been found and issues were scrutinized...
A high bandwidth critical path monitor (1 sample/ cycle at 4-5 GHz) capable of providing real-time timing margin information to a variable voltage/frequency scaling control loop is described. The critical path monitor tracks the critical path delay to within 1 FO2 inverter delay with a standard deviation less than 3 FO2 delays over process, voltage, temperature, and workload. The CPM is sensitive...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.