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A process-insensitive current-controlled delay generator is presented with a large tunable range of the time delay. By adopting process variation compensation techniques in the generation of time delay, the delay generator is able to provide process-insensitive clock pulses. The circuit has been fabricated in 90 nm CMOS technology, consumes 310 μW from a 1.1V supply. Using, in a typical...
Accumulation-mode MOS varactors (AMOSVs) are considered for use in THz frequency multipliers. The superior modulation ratios and lower series loss relative to silicon Schottky diodes for a 130-nm CMOS technology are highlighted. Dynamic cutoff frequencies in excess of 1-THz are predicted. AMOSV potential for 10-dB loss, 600-GHz doublers is discussed as is an integrated 100-GHz doubler design.
This paper propose a multi-standard transceiver architecture, based on 3.6-to-4.4 GHz UWB impulse transmitter and 402-to-405 MHz super-regenerative receiver for medical implant devices. This architecture eliminates the requirement of frequency synthesizer and power amplifier at transmitter side and LNA, mixers, IF amplifiers and ADCs. at receiver side of implant transceiver. The multi-standard external...
This This paper reports a new width tunable ultra wide-band (UWB) Gaussian monocycle pulse (GMP) generator for radar application. The circuit is a monolithic design in low cost CMOS technology and is area efficient. The GMP is generated with a square wave generator and then differentiated. The square wave generator is actually a glitch generator using a ring oscillator as the input. The differentiator...
This paper presents principles and results of dynamic testing of an SRAM-based FPGA using time- resolved fault injection with a pulsed laser. The synchronization setup and experimental procedure are detailed. Fault injection results obtained with a DES crypto-core application implemented on a Xilinx Virtex II are discussed.
Standby power of a 32k ?? 8 pseudo-static RAM has been reduced to 60uA using an expanded internal refresh interval, a reduced oscillating frequency by a back bias generator, and other power saving circuits.
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