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We present the design and implementation of an analog front-end for smart-sensors and measurement results with prototypes of acceleration micro-sensors. The technology used for sensor manufacturing features silicon nanowires as strain gauges. The proposed system supports Kelvin contacts scheme and sensor bias duty-cycling. A fully-differential amplifier with a sensor-degenerated common-mode rejection...
This paper deals with an excess noise sources in concrete materials. The theoretical description is put forward as well as supporting experiments of real samples. Physical variables under consideration are spectral densities of voltage and/or current fluctuation for different sample dimension and electrical excitation. It managed to get information about Johnson-Nyquist noise, 1/f noise and Polarization...
The electromagnetic noise generated by terahertz photoconductive emitters was investigated, and the intensity of noise spectrum was analysed by statistical method. The relationship between the noise of the emitter and the resistivity as well as carrier lifetime of the antenna material was obtained. And the effect of carrier lifetime and mobility of antennas on the THz generation efficiency was investigated.
Modern X-ray imaging applications require low noise and power, high rate readout front-end electronics. A widely used, dedicated for semiconductor detectors analog part of readout front-end architecture consists with charge sensitive amplifier and pulse shaping amplifier. To meet the requirements of pixel applications the simple architectures of front-end electronics and used amplifiers, low power...
Flicker (1/f) noise and TCR are compared for arsenic- and phosphorus-doped polysilicon in a 0.18 μm CMOS base technology. Resistors implanted with arsenic exhibit about 4 times higher noise than with phosphorus at the same dose and thermal budget. The TCR of arsenic-doped polysilicon is negative, near −1065 ppm/K, while that of phosphorus-doped resistors positive, about + 590 ppm/K. The mismatch of...
In this paper, we show the junctionless nanowire FETs (JNTs) with gate length of 20 nm and the conventional inversion mode nanowire FETs (cINTs). The fabricated JNT has shown better electrical characteristics with high Ion / Ioff ratio (>106) and subthreshold slope (∼75 mV/dec) than cINT, which means that the simpler fabrication process without junction formation makes the JNT a promising candidate...
The electric capacity of the condenser whose inside is filled with fullerene C60 is measured using two-phase lock-in amplifier. It is found that both the real part and imaginary part of the permitivity of the fullerene shows 1/f fluctuation in the low frequency area.
Low frequency noise in virgin (not aged) graphene transistors might be relatively low (comparable to average Si MOSFETs), at least for high quality devices with the bottom gate configuration. Graphene channels are the dominant sources of noise, even though the contact resistances have an important effect on the noise magnitude due to the voltage re-distribution between the contacts and the channel...
Three-dimensional (3-D) integration is a promising technology to alleviate the interconnect bottleneck by stacking multiple dies in a monolithic fashion. Both power dissipation and delay can be reduced by utilizing the third dimension where through silicon vias (TSVs) are used for vertical communication. Characteristics of switching noise that couples to a sensitive device due to a TSV are investigated...
A novel SiGe HBT low noise amplifier (LNA) was designed by adopting the feedback resistors, which are low cost and implemented easily in VLSI technology. Due to the absence of on-chip spiral inductor, the die area of this novel LNA decreases noticeably. The novel resistive feedback structure of the LNA comprising a shunt feedback loop and a series feedback loop, wherein the shunt feedback loop is...
In this paper, we present a cost-effective JFET integrated in 0.18μm RFCMOS process. The design is highly compatible with standard CMOS process, therefore can be easily scaled and implemented in advanced technology nodes. The design impact on Ron and Voff is further discussed, providing the insights and guidelines for JFET optimization. Besides the superior flicker noise (1/f noise) characteristics,...
As it was the mechanical noise used for diagnostic of machine in the past, the electronic noise can be used as diagnostic tool for detection defects in electronical devices and systems in the future. This paper deals with comparisons of noise spectroscopy and detection of microplasma noise sources in the three new type of solar cells G1, G3 and G5. When high electric is applied to PN junction with...
In this paper, we introduce the cylindrical coordinate based flicker noise model for Silicon NanoWire Field Effect Transistor (Si-NWFET) with Gate-All-Around (GAA) structure. For the accurate extraction of the volume trap density, Nt, with 1/f noise modeling, the parameters which represent the intrinsic channel properties are determined by rejecting the series resistance Rsd effect. Due to the random...
A new generation of commercial-off-the-shelf (COTS) buck-type converters built using advanced short channel "high voltage" CMOS processes have the potential to operate near the interaction region of the proposed Super Large Hadron Collider (sLHC) upgraded accelerator. The benefit would be a simpler DC power distribution system and an increase of the overall power efficiency by allowing higher...
This paper presents an innovative structure based on 3 dimensional integration technology, where ultra thin inter layer dielectric enables a dynamic threshold voltage (VTH) control. A sequential process flow is proposed to fabricate 3D devices with dynamically tunable VTH. This ability can be exploited to design SRAMs cells with increased stability and surface density compared to planar technology...
Continuous scaling, necessary for enhanced performance and cost reduction, has pushed existing CMOS materials much closer to their intrinsic reliability limits, forcing reliability engineers to get a better understanding of circuit failure. This requires that designers will have to be very careful with phenomena such as high current densities or voltage overshoots. In addition to the reliability issues,...
Novel 3D stacked gate-all-around multichannel CMOS architectures were developed to propose low leakage solutions and new design opportunities for sub-32 nm nodes. Those architectures offer specific advantages compared to other planar or non planar CMOS devices. In particular, ultra-low IOFF (< 20 pA/mum) and high ION (> 2.2 mA/mum) were demonstrated. Moreover, those transistors do not suffer...
In deep submicron era, to prevent larger amount of SRAM from more frequently encountered overheating problems and react accordingly for each possible hotspots, multiple ideal run-time temperature sensors must be closely located and response rapidly to secure system reliability while maintaining core frequency. This paper presented a method to extract run-time temperature information from multiple...
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