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We present our results on the analysis of electrical performance of Flip-Chip bonded thin Silicon chip-on-foil assemblies during bending. A custom made bending machine was utilized to bend the test samples and the electrical resistance of the Daisy Chain structures were measured during the tests. Resistance measurements confirmed the failure of the test samples after about 2000 bending cycles.
In this paper, we review the conditions at which FinFETs could meet system requirements at the 7nm node. We explore the key enablers to meet the power performance targets for 7nm node. We show that the device parasitics is the biggest performance detractor as we scale down. We illustrate the device design space that allows to meet speed and power targets, then explore the optimization of the geometry...
A novel resistive memory with the TiN/Ti/HfOx/TiN stack is proposed and fully integrated with 0.18 μm CMOS technology. The excellent memory performances such as low operation current (down to 25 μA), low operation voltage (<;1.5 V), high ON/OFF resistance ratio (above 100), and fast switching speed (10 ns) have been demonstrated for this ReRAM. Moreover, the device exhibits excellent scalability...
The impact of gate-pitch scaling on device internal and external resistance is examined by advanced process and device modeling including distributed contact resistance model, mechanical stress and Monte Carlo (MC)-based stress-dependent mobility model. The contact resistance components and their major parameters in sub-50nm contact regime are analyzed by TCAD and transmission line modeling (TLM)...
Although a significant effort was made recently in the development of binary oxide based resistive memory (RRAM), reliability issue is still the most concern, but less addressed. By stressing the device in high resistance state (HRS) with constant voltage of the same bias polarity during SET process, the disturbed time is found to exhibit extreme low Weibull slope (~0.3). This characteristic can drastically...
The root causes of the high voltage (HV) LDMOS (Fig. 2) failed at the low voltage electrostatic-discharge (ESD) zap is found. One is caused by the bulk layout and one is caused by the intrinsic characteristic of the device. From the findings, a new structure is proposed to eliminate the root causes without sacrificing the IV characteristics and dimension of the device.
We review the advanced technologies available for enhancing drive current of the high-density planar FETs. From the theoretical expression of the saturation current of the FET, the technologies are categorized into four groups; (1) scaling inversion gate dielectric thickness, (2) mobility enhancement, (3) steep lateral profile of the source/drain extension, and (4) reduction of parasitic resistance...
The use of strained SiGe is essential to improvement in device performance. However, the structure is susceptible to strain relaxation and wafer deformation during thermal annealing. The accumulation of stress in the wafer needs to be controlled to minimize photolithographic overlay errors. Laser spike annealing offers negligible pattern effects, closed-loop temperature control, and localized heating,...
Transconductance (gm) enhancement in n-type and p-type nanowire field-effect-transistors (nwFETs) is demonstrated by introducing controlled tensile strain into channel regions by pattern dependant oxidation (PADOX). Values of gm are enhanced relative to control devices by a factor of 1.5 in p-nwFETs and 3.0 in n-nwFETs. Strain distributions calculated by a three-dimensional molecular dynamics simulation...
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