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This paper reports a novel material/process-based design for reliability-aware Ge gate stack for the first time. Initially good characteristics of Ge gate stacks do not necessarily guarantee the long-term device reliability. To overcome the big hurdle, we have investigated the stability of GeO2 network as well as the formation of new high-k. The very robust Ge gate stack with both 0.5 nm EOT and sufficiently...
In this work, cells behavior during forming is monitored through an incremental pulse and verify algorithm on 4kbit RRAM arrays. This technique allows recognising different cell behaviors in terms of read-verify current oscillation: the impact of these oscillations on reliability and cell-to-cell variability has been investigated during 1k endurance cycles and 100k pulse stress under a variety of...
This paper presents a first comprehensive study of SET speed-disturb dilemma in RRAM using statistically-based prediction methodologies. A rapid ramped-voltage stress based on percolation model and power-law V-t dependence showed excellent agreement with the time-consuming constant-voltage stress, and was applied to evaluate current status of RRAM devices in the literature.
A novel resistive memory with the TiN/Ti/HfOx/TiN stack is proposed and fully integrated with 0.18 μm CMOS technology. The excellent memory performances such as low operation current (down to 25 μA), low operation voltage (<;1.5 V), high ON/OFF resistance ratio (above 100), and fast switching speed (10 ns) have been demonstrated for this ReRAM. Moreover, the device exhibits excellent scalability...
Bias temperature instability of TiN/HfOx/Pt resistive random access memory (ReRAM) device is investigated in this work for the first time. As temperature increases (up to 100°C in this work), it is observed that: (1) leakage current at high resistance state (HRS) increases, which can be explained by the higher density of traps inside dielectrics (related to trap-assistant tunneling), leading to a...
Although a significant effort was made recently in the development of binary oxide based resistive memory (RRAM), reliability issue is still the most concern, but less addressed. By stressing the device in high resistance state (HRS) with constant voltage of the same bias polarity during SET process, the disturbed time is found to exhibit extreme low Weibull slope (~0.3). This characteristic can drastically...
A 30??30 nm2 HfOx resistance random access memory (RRAM) with excellent electrical performances is demonstrated for the scaling feasibility in this work. A 1 Kb one transistor and one resistor (1T1R) array with robust characteristics was also fabricated successfully. The device yield of the 1 Kb array is 100%, and the endurance for these devices can exceed 106 cycles by a pulse width of 40 ns. Two...
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