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Flip chip packaging of ultra fine pitch integrated circuits (ICs) on organic substrates aggravates the stress-strain concerns, requiring a fundamentally different system approach to interconnections, underfill, interfaces, and the substrate. This work demonstrates a novel interconnection solution with excellent reliability for ultra-fine pitch (~30 mum) silicon (Si) on organic first level interconnections...
This paper uses a validated, two-dimensional global underfill flow model previously developed by the authors [1] to examine the effects of substrate surface (ceramic vs. organic) and temperature-dependent underfill viscosity on underfill flow-out time, flow front shape, and void formation during the flip chip encapsulation process. Model predictions are validated by experiments using bumped quartz...
The ultra-small form factor of the electronic components along with a reliable and inexpensive high-density interconnect technology are the key factors in bringing flexible electronics to the next level of miniaturization without compromising performance and substantially increasing production cost. The common thick-film methods used today to fabricate conductive trace patterns on flexible boards...
This paper focused on design, assembly and reliability assessments of 21 ?? 21 mm2 Cu/Low-K Flip Chip (65 nm technology) with 150 ??m bump pitch. Metal redistribution layer (RDL) and polymer encapsulated dicing lane (PEDL) were applied to the chip wafer to reduce the shear stress on the Cu/low-K layers and also the strain on the solder bumps. The first level interconnects evaluated were Pb-free (97...
Nowadays, the demand for the printed wiring board (PWB) of the environment harmony type is rising rapidly. We have developed a new halogen-free material with low coefficients of thermal expansion (CTE), which will be applied to the plastic packages such as FC-BGA and CSP. The original resin system and filler treatment technique named FICS (filler interphase control system) were applied to the material...
Screen-printing is not a new technology in the printed circuit industry. However, the combinations of new paste materials and an advanced screen-printing process further increases the value of printable flexible electronics that cannot be made by the traditional photolithography process with copper foils. Additionally, more functionality from the circuits will be generated with new materials in the...
With the high development of IC industry, the size of IC is reduced and the package density is improved continuously. All of these propose higher requests to package substrate. The development directions of package substrate are miniaturization, ultrathin and multi-layer. Embedded components technology, which includes two types: embedded passive and active components, has applied to package substrate...
A numerical modelling method for the analysis of solder joint damage and crack propagation has been described in this paper. The method is based on the disturbed state concept. Under cyclic thermal-mechanical loading conditions, the level of damage that occurs in solder joints is assumed to be a simple monotonic scalar function of the accumulated equivalent plastic strain. The increase of damage leads...
An on-chip buck converter with 3D chip stacking is proposed and the operation is experimentally verified. The manufactured converter achieves a maximum power efficiency of 62% for an output current of 70mA with a switching frequency of 200MHz and a 2x2mm on-chip LC output filter in 0.35mum CMOS. The use of glass epoxy interposer to increase the maximum power efficiency up to 71.3%, and the power efficiency...
This paper presents an innovative structure based on 3 dimensional integration technology, where ultra thin inter layer dielectric enables a dynamic threshold voltage (VTH) control. A sequential process flow is proposed to fabricate 3D devices with dynamically tunable VTH. This ability can be exploited to design SRAMs cells with increased stability and surface density compared to planar technology...
Continuous scaling, necessary for enhanced performance and cost reduction, has pushed existing CMOS materials much closer to their intrinsic reliability limits, forcing reliability engineers to get a better understanding of circuit failure. This requires that designers will have to be very careful with phenomena such as high current densities or voltage overshoots. In addition to the reliability issues,...
Novel 3D stacked gate-all-around multichannel CMOS architectures were developed to propose low leakage solutions and new design opportunities for sub-32 nm nodes. Those architectures offer specific advantages compared to other planar or non planar CMOS devices. In particular, ultra-low IOFF (< 20 pA/mum) and high ION (> 2.2 mA/mum) were demonstrated. Moreover, those transistors do not suffer...
The polycrystalline samples of BaSi2, SrSi2, and LaSi were prepared by spark plasma sintering (SPS). The electrical resistivity (rho) and Seebeck coefficient (S) were measured above room temperature. The S of BaSi2 was negative and the absolute values were rather high (-669 muVK-1 at 337 K). The S of SrSi2 was positive and the absolute values were lower (118 muVK-1 at 332 K) than those of BaSi2. For...
The present work aims at studying the cooling performance of a thermoelectric device that integrated with integrated heat spreader (IHS) on a flip-chip plastic ball grid array (FC-PBGA) package. The new thermoelectric device herein is fabricated on the metal substrates by flip-chip assembly process. Thermal performance of the new package was comprehensive studied. The thermal resistances of IHS with/without...
In this study, we fabricated in-plane thermoelectric micro-generators (4 mm times 4 mm) based on bismuth telluride thin films by using flash evaporation method. The thermoelectric properties of as-grown thin films are lower than those of bulk materials. Therefore the as-grown thin films were annealed in hydrogen at atmospheric pressure for 1 hour in a temperature range of 200 degC. to 400degC. By...
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