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Resistance uniformities of Au/TiO2/Au memristors with oxide layer of 20-nm-thick, 30-nm-thick and 40-nm-thick have been study respectively. For each device, uniformity of high resistances is much higher than that of low resistances in cycles, no matter how thickness the oxide layer is. It indicates that conductive filaments based on oxygen vacancies are the dominated effect on resistive switching...
This paper reports a novel maskless nanoscale material etching method based on microplasma devices arrays. That is, inverted pyramidal microplasma devices arrays are integrated into the scanning probe tips array to realize maskless nanoscale material etching with advantages of high efficiency, large area and low cost. A 4×4 inverted pyramidal microplasma device array with each microcavity dimension...
There are some benefits for embedded passive devices, such as higher reliability by eliminating the solder joint failure from the surface discrete components, real-estate reduction by reducing the physical size of the printed circuit board assembly (PCBA) surface area, better frequency performance by avoiding the inherent parasitic effects from current surface mount technology (SMT). Definitely, embedded...
We applied microelectromechanical systems technology for producing a new type of transparent touch panel with conductive liquid channels. We used a molding process for fabricating the touch panel and transparent silicone rubber material for producing the channel structures. The height, width, and length of the flow channels were 0.1, 1.0, and 40 mm, respectively, and the pitch of the channels was...
We have developed a on-chip double-shielded quantum Hall device and a double-shielded chip-carrier. The device in conjunction with the carrier will realize impedance standard based on the quantum Hall effect. In this configuration, the Hall bar is covered by separated on-chip shields and shields of the chip carrier to retrieve the leakage current. In this paper, we show detail of the QHR device fabrication...
A new approach to developing, fabricating, and testing chalcogenide-based multi-state phase-change nonvolatile memory (NVM) is presented. A test chip is fabricated through the MOSIS service. Then post processing, in the Boise State University lab, is performed on the chip to add the chalcogenide material that forms the NVM. Each memory bit consists of an NMOS access transistor and the chalcogenide...
An on-chip buck converter with 3D chip stacking is proposed and the operation is experimentally verified. The manufactured converter achieves a maximum power efficiency of 62% for an output current of 70mA with a switching frequency of 200MHz and a 2x2mm on-chip LC output filter in 0.35mum CMOS. The use of glass epoxy interposer to increase the maximum power efficiency up to 71.3%, and the power efficiency...
This paper presents an innovative structure based on 3 dimensional integration technology, where ultra thin inter layer dielectric enables a dynamic threshold voltage (VTH) control. A sequential process flow is proposed to fabricate 3D devices with dynamically tunable VTH. This ability can be exploited to design SRAMs cells with increased stability and surface density compared to planar technology...
To increase memory bandwidth with minimum area overhead, the new concept of 3D-stacked memory structure consisting of a small sense amplifier shared with a few 3D memory cells has been presented. The 16 bit 3D-stacked TiO2 memory chip was fabricated and demonstrated. The estimated bandwidth per unit area of 3D-stacked memory in sub-65 nm CMOS technology indicates that the 3D-stacked memory has potential...
Novel 3D stacked gate-all-around multichannel CMOS architectures were developed to propose low leakage solutions and new design opportunities for sub-32 nm nodes. Those architectures offer specific advantages compared to other planar or non planar CMOS devices. In particular, ultra-low IOFF (< 20 pA/mum) and high ION (> 2.2 mA/mum) were demonstrated. Moreover, those transistors do not suffer...
We present and discuss the fabrication process and the performance of a flexible micro thermoelectric generator with electroplated Bi2+xTe3-x thermocouples in a SU-8 mold. Demonstrator devices generate 278 muWcm-2 at DeltaTmeas=40 K across the experimental set up. Based on model calculations, a temperature difference of DeltaTG=21.4 K across the generator is assumed. Due to the flexible design and...
ldquoDevelopment for advanced thermoelectric conversion systemsrdquo supported by the new energy and industrial technology development organization (NEDO) has been successfully completed as one of the Japanese national energy conservation projects. Three types of the cascaded thermoelectric modules operating up to 850 K in high electrode temperature and two types of Bi-Te thermoelectric modules operating...
We report thermoelectric characterization of Bi2-xSbxTe3 (x = 0.5, 1.0, and 1.5) synthesized by a solvothermal method using DMF as solvent. For Bi2Te3, the size of the edge and thickness of the hexagonal nanoplatelets are 200-250 nm and 20-25 nm, respectively. Bi2Te3 nanosheets appear to grow epitaxially from the surface of the Te tubes, which forms in the first step and acts as the template for the...
In this study, we fabricated in-plane thermoelectric micro-generators (4 mm times 4 mm) based on bismuth telluride thin films by using flash evaporation method. The thermoelectric properties of as-grown thin films are lower than those of bulk materials. Therefore the as-grown thin films were annealed in hydrogen at atmospheric pressure for 1 hour in a temperature range of 200 degC. to 400degC. By...
Sublinear signal propagation delay in VLSI circuits carries a far greater penalty in wire area than is commonly realized. Therefore, the global complexity of VLSI circuits is more layout dependent than previously thought. This effect will be truly pronounced in the emerging wafer scale integration technology. We establish lower bounds on the trade-off between sublinear signalling speed and layout...
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