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This paper shows a methodology to reduce electromagnetic radiation in typical CMOS digital systems from chip PDN design point of view. Total PDN property with anti-resonance peak can be strongly affected by on-die PDN property. Then, in order to suppress anti-resonance peak in total system PDN, design of chip PDN is more effective than off-chip damping method. Then, two similar test chips were designed...
This paper proposes a pulse-controlled common-mode feedback circuit for a supply-scalable fully-differential amplifier. The pulse-controlled common-mode feedback circuit overcomes the large area cost associated with a conventional R-C common-mode feedback circuit while maintaining high gain and large output signal range of the amplifier. The amplifier is implemented in low power/leakage 65nm CMOS...
A 60 GHz double-balanced mixer for direct upconversion using standard 90 nm CMOS technology is reported. The up-conversion mixer comprises an enhanced double-balanced Gilbert cell with current injection for power consumption reduction, and negative resistance compensation for conversion gain (CG) enhancement, a Marchand balun for converting the single LO input signal to differential signal, and another...
In this paper, an inductorless broadband linear-in-dB Variable-Gain Amplifier (VGA) circuit for use in the Square Kilometer Array (SKA) is presented. A two-transistor topology, which realizes a linear-in-dB function, is used to design a differential VGA. The VGA is both input and output power matched to 100Ω differential sources and loads. The design is fabricated in ST 65nm CMOS technology with a...
The non-ideal behaviour of a classical comparator-based first-order relaxation oscillator is analysed. The influences of the comparator slew-rate and output resistance as well as the parasitic resistances of the reactive element are considered. Numerical simulations at system level and transistor level are given.
This paper presents a design and measurements of multichannel integrated circuits dedicated to recording of neurobiological signals. 64 recording channels have been implemented in a single chip using a commercially available CMOS 180 nm process. A single recording amplifier consumes only 25 µW from 1.8 V supply and occupies 0.13 mm2 of the silicon area. Its main parameters such as the low/high cut...
A DC-10.5-GHz CMOS distributed amplifier (DA) with flat and low noise figure (NF), flat and high power gain (S21), and small group delay variation using standard 0.18 μm CMOS technology is demonstrated. Flat and low NF was achieved by adopting the proposed RLC terminal network with 140 Ω terminal resistance at dc and very high frequencies (instead of the traditional 50 Ω terminal resistance or the...
Stack-transistor structure is often used in RF applications for higher power handling capability and/or isolation. LDMOSFET may provide similar advantages with smaller device area and lower series resistance. The purpose of this work is extracting the RF parameters of a LDMOSFET and design a RF switching circuit with these parameters. The design trade-off between LDMOS and CMOS technologies was discussed...
A universal interfacing circuit for resistive-bridge sensing elements and bridge-output-to-frequency and/or duty cycle converters is described in this paper. It is based on a simple, cost effective three-point measuring technique and does not require any additional active components. The designed IC has been realized in a standard CMOS technology as a low power Application Specific Integrated Processor...
An on-chip buck converter with 3D chip stacking is proposed and the operation is experimentally verified. The manufactured converter achieves a maximum power efficiency of 62% for an output current of 70mA with a switching frequency of 200MHz and a 2x2mm on-chip LC output filter in 0.35mum CMOS. The use of glass epoxy interposer to increase the maximum power efficiency up to 71.3%, and the power efficiency...
In this paper, a CMOS analog-to-digital converter (ADC) for Ultra Wide Band (UWB) applications with a 6-bit 1GSPS at 1.8 V is described. The architecture of the proposed ADC is based on a fully folded ADC using resistive interpolation technique for low power consumption. To reduce the power consumption, a folder reduction technique to decrease the number of folding blocks (NFB) is proposed. Further,...
This paper describes a comparative analysis between two topologies of operational amplifiers to design a 40 MS/s 12-bit pipeline analog to digital converter (ADC). The analysis includes AC and transient simulation to select the proper topology. This ADC is implemented in a 0.35 mum AMS CMOS technology with 3.3 V single power supply. The capacitors and selected operational amplifiers were scaled for...
This paper presents a wideband circuit model of silicon-based interconnects for predicting their metallic and silicon substrate losses at higher frequencies. The skin and proximity effects in the structure are characterized using the partial element equivalent circuit (PEEC) method, and the parasitic parameters in silicon substrate are captured according to some analytical equations. Good agreements...
The next generation of wireless communication is a ubiquitous radio system concept, providing wireless access from short-range to wide-area, with one single reconfigurable and adaptive system for all envisaged radio environments. This paper presents the design approach of RCO (reconfigurable concurrent oscillator) that simultaneously generates two or more signals of different frequencies that eliminate...
A high intercept points, cost-effective, and power-efficient switching FET double balanced mixer (DBM) is reported. The Switching FET DBM demonstrated in this work offers input intercept points (IIP3) and conversion loss typically 44 dBm and 8.5 dB respectively with 15 dBm LO power for the frequency band (RF: 900-2150 MHz, LO: 850-1950 MHz, IF: 50-200 MHz). The measured interport isolation is typically...
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