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This paper presents a fully pipelined layered decoder architecture for IEEE 802.11 n/ac/ax LDPC codes, free of idle cycles. Several decoder architectures for such codes have emerged in the literature featuring throughputs in the multi- Gbps range. The proposed architecture surpasses the highest reported throughput for IEEE 802.11 n/ac/ax LDPC codes. This is achieved 1) algorithmically, by implementing...
Pipelined layered decoder (PLD) of quasi-cyclic low-density parity-check (QC-LDPC) codes is one of most popular high-throughput decoder in modern communication systems. However, the traditional QC-LDPC codes are not suitable for PLD and lead to memory access conflict problems (MACPs) that reduce the throughput of PLD. Therefore, an efficient layered block progressive edge-growth (EL-BPEG) algorithm...
Nonbinary LDPC codes have shown superior performance, but decoding nonbinary codes is complex, incurring a long latency and a much degraded throughput. We propose a low-latency variable processing node by a skimming algorithm, together with a low-latency extended min-sum check processing node by prefetching and relaxing redundancy control. The processing nodes are jointly designed for an optimal pipeline...
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