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8 T bit-cells hold great promise for overcoming device variability in deeply scaled SRAMs and enabling aggressive voltage scaling for ultra-low-power. This paper presents an array architecture and circuits with minimal area overhead to allow column-interleaving while eliminating the half-select problem. This enables sense-amplifier sharing and soft-error immunity. A reference selection loop is designed...
This paper presents two security strategies for resisting physical attack utilizing data remanence of SRAM in powered-off state. Secure circuits including power supply, power supply selector, powered-off detector, and erase or rewrite circuit are integrated into conventional SRAM to realize erase or rewrite operations and avoid being disassembled by attackers. Implemented with 0.25 ??m HHNEC CMOS...
A novel SRAM architecture with a high density cell in low supply voltage operation is proposed. A self-write-back sense amplifier realizes cell failure rate improvement by more than two orders of magnitude at 0.6 V. A cascaded bit line scheme saves additional process cost for hierarchical bit line layer. A test chip with 256 kb SRAM utilizing 0.495 um2 cell in 65 nm CMOS technology demonstrated 0...
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