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A new asymmetrical ground gated 7T SRAM circuit technique is presented in this paper to lower leakage currents and enhance noise immunity in idle memory banks. A novel write assist scheme is proposed to enhance write margin with the new memory circuit. The leakage power consumption is suppressed by up to 4.30× and the data stability is enhanced by up to 4.79× as compared with the previously published...
An 8T SRAM fabricated in 45 nm SOI CMOS exhibits voltage scalable operation from 1.2V down to 0.57V with access times from 400 ps to 3.4 ns. Timing variation and the challenge of low voltage operation are addressed with an AC-coupled sense amplifier. An area efficient data path is achieved with a regenerative global bitline scheme. Finally, a data retention voltage sensor has been developed to predict...
SCMOS is a low cost, high capacity, high speed, high yield, and power saving VLSI device platform technology for microelectronics chips and modules. Benefits include: (1) Uses the complementary Low threshold Schottky Barrier Diodes (LtSBD or simply SBD). (2) Integrated the SBD and CMOS transistor as basic circuit elements for Analog, Logic, and Memory (ALM) macros. (3) Single power supply chip. Circuits...
A low-voltage high-speed bulk-CMOS SRAM that operates over 100MHz at 0.5V, for the first time, is proposed. A novel 8-transistor (8T) memory cell with a complementary read port (C-RP) improves the read speed by enabling differential bit-line sensing, while the conventional 8T SRAM drives the bit line with a single read port (S-RP). The cell layout of the C-RP SRAM has point symmetry and a small area...
This paper presents a configurable SRAM with 0.149 ??nf cell in 32 nm high-k metal-gate CMOS. Constant-negative-level write buffer adjusts bitline level automatically for configuration range of four to 512 cells/bitline, improving write margin at low voltage. Measurement results demonstrate that cell-failure-rate improves by two orders of magnitude at 0.5 V.
The goal of this paper is to reduce the power and area of the Static Random Access Memory (SRAM) array while maintaining the competitive performance. Here the various configuration of SRAM array is designed using both the six-transistor (6T) SRAM cell and a new loadless four-transistor (4T) SRAM cell in deep submicron (130nm, 90nm and 65nm) CMOS technologies. Then it is simulated using HSPICE to check...
CMOS technology has followed Moore's law into the nanoscale regime where SRAM scaling is facing increasing challenges in gaining performance at reduced leakage power for future product applications. Despite the advances in process technologies and the resultant ability to produce ever-smaller feature sizes, the increasing variations of scaled devices in SRAM are playing an increasingly important role...
A 512 Kb dual-power-supply SRAM is fabricated in 40nm CMOS with 0.179 mum2 cell, which is 10% smaller than the SRAM scaling trend. The smaller cell size is realized by channel area saving. To improve the cell stability of the small channel area cell, we use a WL level-control scheme generated from dual power supplies in the WL driver. An adaptive WL-level programming scheme and dynamic-array-supply...
The minimum operating voltage (Vmin) of nano-scale LSIs is investigated, focusing on logic gates, SRAM cells, and DRAM sense amplifiers in LSIs. The Vmin that is governed by SRAM cells rapidly increases as devices are miniaturized due to the ever-larger variation of the threshold voltage (VT) of MOSFETs. The Vmin, however, is reduced to the sub-one-volt region by using repair techniques and new MOSFETs...
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