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Simulation is a fast, controlled, and reproducible way to evaluate new algorithms for distributed computing platforms in a variety of conditions. However, the realism of simulations is rarely assessed, which critically questions the applicability of a whole range of findings. In this paper, we present our efforts to build platform models from application traces, to allow for the accurate simulation...
Ring Oscillator (RO) Physical Unclonable Function (PUF) is one of the most popular silicon PUFs which exploit manufacturing variations during the chip fabrication process. RO PUF can generate secret bits by comparing the frequency difference between two ROs. However, previous RO PUFs improve flexibility and reliability through adding redundant ROs and thus incur unacceptable hardware overheads. In...
The network function virtualization-enabled multicast problem includes constructing traffic forwarding topology, deploying required functions and steering traffic through them. Currently, jointly taking them into consideration is still an open problem and we propose a multi-stage solution to solve it. Specifically, we separate the multicast traffic forwarding and function delivery. The traffic forwarding...
Technology scaling along with unprecedented levels of device integration has led to increasing numbers of analog/mixed-signal/RF design bugs escaping into silicon. Such bugs are manifested under specific system-on-chip (SoC) operating conditions and their effects are difficult to predict a-priori. This paper describes recent advances in detecting and diagnosing such bugs using "guided" stochastic...
This paper proposes a highly defect tolerant Parallel Prefix Adder (PPA) design. Motivated by the inherent defect tolerance capability displayed in a Kogge Stone Adder (KSA), this paper identifies the key elements that can be applied to make the general PPA's defect tolerant: 1) the Generate and Propagate computing hardware is divided into disjoint groups, such that defects in one group will not “contaminate”...
While sub/near-threshold design offers the minimal power and energy consumption, such approach strongly deteriorates circuit performances and robustness against PVT (process/voltage/temperature) variations, leading to gigantic speed penalties and large silicon areas. Inexact and approximate circuit design can address these issues by trading calculation accuracy for better silicon area, circuit speed...
Inexact and approximate circuit design is a promising approach to improve performance and energy efficiency in technology-scaled and low-power digital systems. Such strategy is suitable for error-tolerant applications involving perceptive or statistical outputs. This paper presents a novel architecture of an Inexact Speculative Adder with optimized hardware efficiency and advanced compensation technique...
This paper presents a unified logic for flagged prefix addition-subtraction that eliminates the need to perform constant addition and subtraction in two separate blocks. The logic is based on a modified algorithm for constant subtraction that allows us to achieve the unification which is not possible with traditional algorithms. Thus we are able to eliminate the most crucial challenge that practical...
This paper portrays the selection of hardware unit architectures to be implemented in the new LNS based on a 32bit system. The implementations of the LNS multiply and divide only require a FXP adder, while the LNS addition and subtraction function comprised of several memories, FXP adders and multipliers together with other supporting logics. Thus, in choosing the best FXP adders and multipliers,...
In this paper, we address a new security problem in the realm of collaborating sensor networks. By collaborating sensor networks, we refer to the networks of sensor networks collaborating on a mission, with each sensor network is independently owned and operated by separate entities. Such networks are practical where a number of independent entities can deploy their own sensor networks in multi-national,...
This paper compares 130nm custom silicon implementations of three scalable Montgomery multiplier architectures to previously published FPGA implementations of the same architectures. It investigates the delay, energy, and area tradeoffs of parallelized left-shifting radix-2, radix-4, and Booth-encoded radix-4 architectures. The radix-4 architecture is most efficient, performing 256 × 256-bit modular...
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