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Low swing clocking is a low power design methodology that scales the clock voltage to decrease power consumption of the clock distribution networks, with an expected degradation in the performance. In this work, a novel low swing clock tree synthesis methodology is combined with a custom low swing clock-aware D flip-flop (DFF) design. The low swing clocking serves to reduce the power dissipation whereas...
This paper presents an industry experience and research-based analysis of issues that the deployment of PTP as a service is facing in the finance industry, based on real life examples from a global stock exchange operator. It aims to summarise over three years of author's experience with deploying PTP, highlighting the most common problems encountered: standard specific, implementation specific and...
Packet-based methods for transporting timing information are becoming increasingly important as networks shift from circuit-switched to packet-switched architectures. The packet-delay variation inherent in packet networks is a primary source of clock noise. This paper addresses suitable methods for analyzing Packet Delay Variation (PDV) and the impact on synchronization. Metrics appropriate for analysis...
ICx Radiation, Inc. has implemented a novel timing method for use in a Compton telescope that is capable of nanosecond timing resolution. A critical task in Compton telescope design is to minimize the timing variance between detectors in a large array in order to reduce the background. The voxelSPEC has been developed to combine precise timing with pulse processing electronics in a single device,...
In the CAN bus, mistakes in bit timing will lead to serious decline in bus performance. How to deal with the bit timing of CAN bus communication decided whether the CAN controller can receive or transmit data correctly. According to bus protocol, bit synchronization will fix bit errors resulting from improper setting in many cases. This paper illustrated the structure of nominal bit time and the principle...
In this paper we propose a scheme for enhancing the timing performance of a pre-designed synchronous sequential circuit. In the proposed scheme, a circuit is driven by two clocks. One of them is the conventional clock while the other one, having a shorter period, is applied when the circuit stabilizes well before the critical delay. We use a symbolic algorithm to analyze the timing behavior of the...
A critical function required in most all digital communication systems is synchronization. Three levels of synchronization include carrier phase, spreading code timing, and symbol timing estimation. Digital phase phase-locked loops (DPLLs), are often used to implement these functions. Multirate DPLLs are often found in practice where the timing error detector (TED) or phase detector (PD) operates...
In general-synchronous framework, in which the clock is distributed periodically to each register but not necessarily simultaneously, the circuit performance such as the clock period is expected to be improved by delay insertion. However, if the amount of inserted delays is too much, then the circuit is changed too much and the circuit performance might not be improved. In this paper, we propose an...
The true Cramer-Rao bound (CRB) for the variance of unbiased, data-aided symbol-timing estimate has been obtained from linearly modulated waveforms through an additive white Gaussian noise channel with random carrier phase already. However, in practice, it is unusual to perform carrier synchronization prior to timing recovery. In this paper, we deduce the true CRB for data-aided time delay and frequency...
In this paper, a parallel interpolation structure for all-digital receiver is proposed. Unlike the existing serial interpolation method, which makes timing-adjustment for one sample at a time, the single-symbol parallel interpolation makes timing adjustment for one symbol at a time. This trait lightens the hardware-constraint to the processing rate of the interpolator, and in turn, improves the processing...
In mainstream ASIC design, industry standard automation tools are used in generating circuit implementations that satisfy the timing and power budgets. A typical timing budget follows the specifications of a clock frequency governed by the longest data path in the circuit. To satisfy this constraint, a zero-skew clock network that minimizes or bounds the clock skew is synthesized. Due to variations,...
Time and frequency alignment is critical for ensuring QoS for applications such as voice, real-time video, wireless hand-off, and data over a converged access medium. To satisfy the accuracy of time synchronization, propagation delay measurement is required between time-sensitive devices. There is existing network technology for time synchronization, such as network time protocol (NTP), IEEE 1588...
Clock synchronization among the nodes of wireless sensor networks (WSN) is important for many of its applications but this task becomes quite complex due to their special characteristics. To achieve this goal of clock synchronization, there have been many protocols and algorithms presented so far all of which rely on some kind of timing message exchange among the nodes to be synchronized. In this...
A high bandwidth critical path monitor (1 sample/ cycle at 4-5 GHz) capable of providing real-time timing margin information to a variable voltage/frequency scaling control loop is described. The critical path monitor tracks the critical path delay to within 1 FO2 inverter delay with a standard deviation less than 3 FO2 delays over process, voltage, temperature, and workload. The CPM is sensitive...
In time synchronization, poor stability of cheep crystal oscillator would wipe out all the efforts on reducing synchronization error while the cost of high stability crystal oscillator limits the using scope of measurement and control system. Therefore, the paper proposes a new analysis for time synchronization algorithms that compensating the drift of local clock by the use of timestamp stream, and...
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