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A TSMC 0.35 um CMOS 2P4M process PLL (phase-locked loop) for ISM band applications is proposed. The PLL, with a crossed-coupled pMOS ring-oscillator VCO, is realized without using any inductor. Measurement results show that at the supply voltage of 3.3 V and the lowest reference frequency of 25 MHz, the locking range is from 1.8 GHz to 3.29 GHz, locking time is less than 3 us and the phase noise is...
In this paper, we have presented a phase loop for controlling a chain of gm-C all-pass filters. It's called Delay Locked Loop for Analog Signal Processing, and it's used for signal's phase regulation. 0.35 ??m CMOS technology was used for design and verification of the circuit. According to the obtained results, we have concluded that it is possible to obtain a phase regulation in a wide frequency...
In this paper, a charge-pump based phase-locked loop (CPLL) that can achieve fast locking and tiny deviation is proposed and analyzed. A lock-aid circuit is added to achieve fast locking of the CPLL. Besides, a novel differential charge pump which has good current matching characteristics and a PFD with delay cell has been used in this PLL. The proposed PLL circuit is designed based on the 0.35 um...
In conventional CMOS charge pump circuits, there are some current mismatching characteristics which result in a phase offset in phase-locked loop circuits. This paper presents a new charge pump circuit after detailed analysis of the current mismatch problem. It combines an error amplifier with reference current sources to achieve good current matching characteristics and lower phase noises, and at...
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