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This paper introduces new charge and discharge paths to speed up the turn-on and turn-off process of bootstrapped switch. In the mean time, linearity is improved without increasing capacitance or area. The proposed switch is designed in SMIC 65nm CMOS process and the results indicate that total harmonic distortion (THD) of 95dB is acquired when 103MHz input signal is sampled at 1Gsps.
This paper presents a highly linear CMOS active balanced down-conversion mixer in a TSMC 0.18 μm process for 2.4 GHz application. The proposed mixer uses the current bleeding technique and an extra LC filter to improve the noise figure (NF) and linearity. Also, with an extra LC filter in switching stage and the careful choosing of transistor sizes, the mixer has a better performance in term of IIP3,...
In this paper, a sample/hold circuit for switched capacitor structure in 0.35 ??m CMOS process technology is described. The sample/hold circuit is used for 14-bit pipelined A/D converter with a conversion rate up to 80 MSPS. In the circuit, the differential unity gain structure is employed. The impact of channel injected charges is reduced through sequential control. The amplifier with a folded cascode...
An on-chip buck converter with 3D chip stacking is proposed and the operation is experimentally verified. The manufactured converter achieves a maximum power efficiency of 62% for an output current of 70mA with a switching frequency of 200MHz and a 2x2mm on-chip LC output filter in 0.35mum CMOS. The use of glass epoxy interposer to increase the maximum power efficiency up to 71.3%, and the power efficiency...
While the CMOS analog circuits can be designed with the minimum-gate-length of the fabrication process in the alpha-power law MOSFET model, the length of a MOSFET gate has been chosen to be a larger scale than the minimum-gate-length in the conventional Shockleypsilas square model. In this paper, we describe a 6-b 100 MSPS CMOS current steering digital-to-analog converter (DAC) with the alpha-power...
A double-pole double-throw SOI CMOS switch is presented, which can be exploited to bypass a power stage in a radio transmitter with the aim of improving efficiency in applications requiring transmit power control. The switch is designed through transistors stacking. It is able to manage up to a 35 dBm input power with less than 0.35 dB insertion loss from 500 MHz through 3 GHz. A series-shunt topology...
A high intercept points, cost-effective, and power-efficient switching FET double balanced mixer (DBM) is reported. The Switching FET DBM demonstrated in this work offers input intercept points (IIP3) and conversion loss typically 44 dBm and 8.5 dB respectively with 15 dBm LO power for the frequency band (RF: 900-2150 MHz, LO: 850-1950 MHz, IF: 50-200 MHz). The measured interport isolation is typically...
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