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We present a new low-cost technique for detecting gate-oxide early-life failures (ELF) to overcome reliability challenges in robust systems without requiring expensive concurrent error detection. Our approach is enabled by an on-chip clock control technique, applied during periodic on-line self-test and diagnostics, to detect delay shifts over time before functional failures occur. Using 90 nm test...
In synchronous circuit designs, clock skew is difficult to minimize because a single physical layout of a clock tree must satisfy multiple constraints in a complicated power mode environment where certain modules may operate with different voltages. In this paper, we use adjustable delay buffers (ADB) whose delays can be tuned or adjusted to minimize clock skew under different power modes. Assuming...
In this paper we address the effects of process variations on the performance of clocked storage elements. Two types of structures are selected and evaluated by using energy-delay space analysis. The delay variations of the energy-efficient designs for each clocked storage element are measured and compared. We show how much topology selection is important in order to minimize the impact of process...
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