The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
In this work, the electrical isolation of nanowires fabricated on bulk wafers is investigated. It is shown that electrical isolation can be realized with a Ground Plane isolation implant at the beginning of the process flow. For transistors using extensions, it is seen that a relatively high dose of Ground Plane doping is needed in order to avoid punchthrough through a parasitic channel less controlled...
We have proposed gate-all-around Silicon nanowire MOSFET (SNWFET) on bulk Si as an ultimate transistor. Well controlled processes are used to achieve gate length (LG) of sub-10nm and narrow nanowire widths. Excellent performance with reasonable VTH and short channel immunity are achieved owing to thin nanowire channel, self-aligned gate, and GAA structure. Transistor performance with gate length of...
In this work, we report on the fabrication and characterization of voltage-programmable (VP) nanowire (NW) field-effect-transistor (FET) devices suitable to extend the flexibility in circuit design, i.e. of reconfigurable logic. Ultra-thin silicon NW-structures with mid-gap Schottky S/D junctions on silicon-on-insulator (SOI) substrate have been fabricated as dopant free unipolar CMOS transistors...
We present a simulation study of Si nanowire (NW) transistor devices for logic applications using an atomistic tight-binding (TB) model for the electronic structure calculation, self consistently coupled to a two-dimensional Poisson solver for the solution of the electrostatics. A semiclassical ballistic model is used for the transport calculation. The average carrier velocity and the capacitance...
In this paper, sub-10 nm gate-all-around (GAA) CMOS silicon nanowire field-effect transistors (SNWFET) on bulk Si substrate are fabricated successfully for the first time with 13-nm-diameter silicon nanowire channel. On-state currents of 1494/1054 muA/mum at off leakage currents of 102/6.44 nA/mum are obtained for N/PMOS, respectively. The impacts of nanowire diameter (DNW) and gate oxide thickness...
In this article, we proposed a novel SOI technology for introducing thin BOX SOI structure into bulk Si wafer and demonstrated thin body SOI transistors with the thinnest BOX thickness of 7 nm ever reported. Owing to thin BOX and thin body structure, they showed good VTH controllability and effective ION/IOFF controllability exceeding thick BOX transistors. Their small variation was also confirmed...
In this work the charge-based capacitance measurement (CBCM) method has been extended and calibrated to measure sub-fF level bias-dependent capacitance of single channel silicon nanowire (SNW) transistors. Mixed mode simulations are used to establish the efficacy of the method. Test keys have been carefully designed and fabricated on-chip so that C-V and I-V characteristics are measured on the same...
In this work, fabrication of TSNWFET on SOI with down to 25-nm TiN surrounding gate and 8-nm silicon nanowires is reported with high manufacturability and improved device reliability including reduced junction and gate leakage currents by fully eliminating the bottom parasitic channel existing in previous TSNWFET on bulk Si. And high performance is also obtained to be 1124muA/mum and 1468muA/mum at...
Novel 3D stacked gate-all-around multichannel CMOS architectures were developed to propose low leakage solutions and new design opportunities for sub-32 nm nodes. Those architectures offer specific advantages compared to other planar or non planar CMOS devices. In particular, ultra-low IOFF (< 20 pA/mum) and high ION (> 2.2 mA/mum) were demonstrated. Moreover, those transistors do not suffer...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.