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Threshold logic, a more compact Boolean representation compared to conventional logic gate representation, re-attracted substantial attention from researchers due to the advances of threshold logic implementations with novel nanoscale devices. For the compact representation to be promising, a fast and effective method for transforming a conventional Boolean logic network into a threshold logic network...
The paper presents a new structural fault collapsing method with linear algorithmic complexity to reduce the search space for test generation and fault diagnosis in digital circuits. The method is based on the two phase topology analysis of the circuit description. The first phase of fault collapsing is carried out on the gate level during superposition of Binary Decision Diagrams (BDD) of logic gates,...
Checking for the functional equivalence between two models of a design is a crucial step in a hierarchical transformation based design flow, in which a designer obtains low level implementation models by manual or automatic translation from higher level specification models. Some of the most difficulty tasks CAD users face are the evaluation, comparison and compatibility-issue for different formats...
The voting gate, or k-out-of-n (k/n) gate, is a standard logic gate used in fault trees modelling fault-tolerant systems. It is traditionally expanded into a combination of AND and OR gates, and this expansion may result in combinatorial explosion problem in the calculation of minimal cut sets (MCSs) of the fault tree for even a not very big n, especially when the voting gate inputs are intermediate...
Reversible logic is a key technique for quantum computing so leading to low-power designs. However, current synthesis algorithms for reversible circuits are low efficiency and do not obtain optimized reversible circuits, so they are only applied to small logic functions. In this paper, we propose a new method based on positive Davio expansion to synthesize reversible circuits, which generates a positive...
In this work, we analyzes the relationship between randomly generated Boolean function complexity and the number of nodes in benchmark circuits using the Binary Decision Diagrams (BDD). We generated BDDs for several ISCAS benchmark circuits and derived the area complexity measure in terms of number of nodes. We demonstrate that the benchmarks and randomly generated Boolean functions behave similarly...
The paper presents a new structural fault-independent fault collapsing method for test generation based on the topology analysis of the circuit, which has linear complexity. Fault collapsing is carried out by superposition of binary decision diagrams (BDD) for logic gates, which is used for constructing structurally synthesized BDDs (SSBDD). A new class of SSBDDs with multiple inputs (SSMIBDD) is...
The paper presents a new structural fault-independent fault collapsing method based on the topology analysis of the circuit, which has linear complexity. The minimal necessary set of faults as the target objective for test generation is found. The main idea is to produce fault collapsing concurrently with the construction of structurally synthesized binary decision diagrams (SSBDD) used for test generation,...
For a dynamic fault tree (DFT) that models dynamic system, the occurrence of top event depends on not only the combination of basic events, but also on the occurrence order of basic events. Cut sequence is a set of basic events that fail in a particular order that can induce top event. Cut sequence set (CSS) model uses cut sequences to analyze the dynamic behaviors of dynamic systems, and if includes...
The minimization of logic gates is needed to simplify the hardware design area of programmable logic arrays (PLAs) and to speed up the circuits. The VLSI designers can use minimization methods to produce high speed, inexpensive and energy-efficient integrated circuits with increased complexity. Quine-McCluskey (Q-M) is an attractive algorithm for simplifying Boolean expressions because it can handle...
This paper proposes a framework that improves reversible logic synthesis by employing a dynamically determined variable order for quantum multiple-valued decision diagrams (QMDD). We demonstrate our approach through augmentation of the Miller-Maslov-Dueck (MMD) algorithm that processes the complete function specification in lexicographical order with our technique. We represent and minimize the complete...
Current logic synthesis techniques are ineffective for arithmetic circuits. They perform poorly for XOR-dominated circuits, and those with a high fan-in dependency between inputs and outputs. Many optimizers, therefore employ libraries of hand-optimized arithmetic components, but cannot optimize across component boundaries. To remedy this situation, we introduce a new logic synthesis algorithm which...
This paper presents a new implication tool (Vimplic) which can be used to improve SAT-based combinational equivalence checking. This tool quickly builds the implication graph of the miter circuit and traverse through it inferring implications among its nodes assignments. This set of implications and the miter circuit netlist are converted to conjunctive normal form (CNF) and submitted to the SAT solver...
One effective fault injection approach involves instrumenting the RTL in a controlled manner to incorporate fault injection, and evaluating the behaviour of the faulty RTL whilst running some benchmark programs. This approach relies on checking the effects of faults whilst the design is executing a specific binary image, and therefore the true impact of the fault is limited by the shadow of the program...
Multi-core SoC created great opportunities to increase overall system performance while keeping the power in check but also created many design challenges that designers must now overcome. The challenge of doubling performance every two years used to drive superscalar design with more functional units running concurrently or deeper pipeline racing for highest frequency at the cost of higher power...
This paper presents a hypergraph partitioning based constraints decomposition procedure to guide an RTL satisfiability solver. The constraints with their correlative variables drawn from the RTL circuit are modeled as a hypergraph and techniques based on hypergraph partitioning are employed to decompose constraints. This scheme solves the partitioned problems respectively and reconciles them via cut-set...
Zero-day attacks - especially those that hide the attack exploit by using code obfuscation and encryption - remain a formidable challenge to existing network defenses. Many techniques have been developed that can address known attacks and similar new attacks that may arise in the future. Some methods, like Earlybird and Polygraph, focus on string-based content prevalence in payloads; others focus...
We present techniques for parallel divide-and-conquer, resulting in improved parallel algorithms for a number of problems. The problems for which we give improved algorithms include intersection detection, trapezoidal decomposition (hence, polygon triangulation), and planar point location (hence, Voronoi diagram construction). We also give efficient parallel algorithms for fractional cascading, 3-dimensional...
In this note some aspects of the average behavior of the well known sorting algorithm heapsort are investigated. There are two different methods to construct heaps, which are due to Williams, and to Floyd, and for both methods the respective distribution of the heaps is computed in a continuous model. For Floyd's method moreover the expected number of interchanges, and comparisons which are necessary...
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